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Overview
Bits'n'Bites. A long standing misconception that dates back to the RISC vs CISC debate of the 1980’s is that CISC ISA:s yield better machine code density than RISC ISA:s. At the time that was mostly true, but today (2022) the situation is different and such claims are no longer automatically true.
News
A spatial domain variable block size luma dependent chroma compression algorithm
In this article I will describe a technique that can often compress the chroma data of an image to less than 0.5 bits per pixel on average, without visible artifacts. What is chroma? A common technique in the field of image and video compression is to con
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Debunking CISC vs RISC code density
A long standing misconception that dates back to the RISC vs CISC debate of the 1980's is that CISC ISA:s yield better machine code density than RISC ISA:s. At the time that was mostly true, but today (2022) the situation is different and such claims are
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Report
Getting started with MRISC32
This is a quick introduction to software development for the MRISC32 architecture. The MRISC32 architecture is a novel 32-bit Vector/RISC instruction set architecture, designed to be efficient, powerful, forward looking and easy to work with. It is also o
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I want to show a thing (C++ to machine code)
If you are like me and spend a lot of time looking at assembly language output from compilers, this article may not provide much new information. If not, however, you will hopefully find it interesting. The thing I want to show is how seemingly lengthy an
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Three fundamental flaws of SIMD ISA:s
According to Flynn's taxonomy SIMD refers to a computer architecture that can process multiple data streams with a single instruction (i.e. "Single Instruction stream, Multiple Data streams"). There are different taxonomies, and within those several diffe
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MRISC32 - Stabilizing the Base architecture
The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it an
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MC1: A custom computer with a custom CPU based on a custom ISA
Here is a short report on the current state of my MC1 project, which is an SoC design for FPGA:s. The MC1 is a custom computer that is mainly used for testing and proving the MRISC32 ISA. Currently the main features of the computer are: It is based around
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Ideas for MRISC32 vector operations
This time I want to talk about some future directions for the MRISC32 vector model. For a recap, see: The MRISC32 - A vector first CPU design. The vector model that was chosen for the MRISC32 instruction set architecture has already proven itself successf
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MRISC32 conditional moves
I recently implemented support for conditional move (or more precisely, conditional select) for the MRISC32 ISA, and I wanted to share some thoughts on that. It's one of those pieces that just fit into the MRISC32 ISA puzzle very nicely. Edit: Some parts
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IEEE 754 suggestion: A "core" subset
I've been developing software for over 30 years, and during those years I have frequently come across problems relating to a few features of the IEEE 754 floating point standard, namely: Denormalized numbersConfigurable rounding modes Recently I have also
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