{"company":{"id":668982,"name":"Celerocommunications","domain":"celerocommunications.com","url":"https://alion.io/company/celerocommunications"},"answer":"Celerocommunications builds mostly with Python, MATLAB, Perl, Verilog. Its stack also includes GitHub, UVM, Linux. Python is named in 22 of the 24 job postings Celerocommunications published in the last 12 months (92%). Counted by Alion from the job postings of Celerocommunications, updated Oct 3, 2026.","window_days":365,"postings_analysed":24,"open_postings":15,"technologies_in_use":19,"modernity_score":67,"ai_adoption":false,"technologies":[{"name":"Python","layer":"languages","postings":22,"share":0.9167,"required":15,"open_postings":14,"first_seen":"2026-03-17","last_seen":"2026-09-21","median_stated_pay_usd":250000},{"name":"Cadence Pegasus","layer":"tools","postings":12,"share":0.5,"required":12,"open_postings":6,"first_seen":"2026-06-12","last_seen":"2026-09-21","median_stated_pay_usd":250000},{"name":"Cadence Virtuoso","layer":"tools","postings":9,"share":0.375,"required":1,"open_postings":5,"first_seen":"2026-04-06","last_seen":"2026-09-21","median_stated_pay_usd":250000},{"name":"Siemens Calibre","layer":"tools","postings":6,"share":0.25,"required":6,"open_postings":4,"first_seen":"2026-06-12","last_seen":"2026-09-21","median_stated_pay_usd":250000},{"name":"MATLAB","layer":"languages","postings":6,"share":0.25,"required":1,"open_postings":6,"first_seen":"2026-03-17","last_seen":"2026-08-22","median_stated_pay_usd":225000},{"name":"Perl","layer":"languages","postings":5,"share":0.2083,"required":5,"open_postings":3,"first_seen":"2026-06-12","last_seen":"2026-09-21","median_stated_pay_usd":250000},{"name":"Verilog","layer":"languages","postings":5,"share":0.2083,"required":3,"open_postings":5,"first_seen":"2026-03-17","last_seen":"2026-09-16","median_stated_pay_usd":null},{"name":"SystemVerilog","layer":"languages","postings":3,"share":0.125,"required":3,"open_postings":3,"first_seen":"2026-08-22","last_seen":"2026-09-16","median_stated_pay_usd":null},{"name":"Formal Verification","layer":"tools","postings":2,"share":0.0833,"required":2,"open_postings":2,"first_seen":"2026-08-22","last_seen":"2026-08-22","median_stated_pay_usd":null},{"name":"Synopsys IC Validator","layer":"tools","postings":2,"share":0.0833,"required":2,"open_postings":2,"first_seen":"2026-09-21","last_seen":"2026-09-21","median_stated_pay_usd":null},{"name":"UVM","layer":"frameworks","postings":2,"share":0.0833,"required":2,"open_postings":2,"first_seen":"2026-08-22","last_seen":"2026-08-22","median_stated_pay_usd":null},{"name":"C++","layer":"languages","postings":2,"share":0.0833,"required":0,"open_postings":2,"first_seen":"2026-03-17","last_seen":"2026-03-17","median_stated_pay_usd":null},{"name":"GitHub","layer":"cloud","postings":2,"share":0.0833,"required":0,"open_postings":2,"first_seen":"2026-03-17","last_seen":"2026-03-17","median_stated_pay_usd":null},{"name":"VHDL","layer":"languages","postings":2,"share":0.0833,"required":0,"open_postings":2,"first_seen":"2026-03-17","last_seen":"2026-03-17","median_stated_pay_usd":null},{"name":"Linux","layer":"cloud","postings":1,"share":0.0417,"required":1,"open_postings":1,"first_seen":"2026-09-16","last_seen":"2026-09-16","median_stated_pay_usd":null},{"name":"Microsoft Entra ID","layer":"cloud","postings":1,"share":0.0417,"required":1,"open_postings":0,"first_seen":"2026-09-06","last_seen":"2026-09-06","median_stated_pay_usd":null},{"name":"Synopsys TestMAX","layer":"tools","postings":1,"share":0.0417,"required":1,"open_postings":1,"first_seen":"2026-09-16","last_seen":"2026-09-16","median_stated_pay_usd":null},{"name":"Tessent","layer":"tools","postings":1,"share":0.0417,"required":1,"open_postings":1,"first_seen":"2026-09-16","last_seen":"2026-09-16","median_stated_pay_usd":null},{"name":"VPN","layer":"practices","postings":1,"share":0.0417,"required":1,"open_postings":0,"first_seen":"2026-09-06","last_seen":"2026-09-06","median_stated_pay_usd":null}],"own_products":[],"changes":{"first_appeared":[{"name":"Synopsys IC Validator","first_seen":"2026-09-21"},{"name":"SystemVerilog","first_seen":"2026-08-22"},{"name":"Formal Verification","first_seen":"2026-08-22"},{"name":"UVM","first_seen":"2026-08-22"}],"rising":[],"falling":[],"not_seen_180d":[{"name":"C++","last_seen":"2026-03-17"},{"name":"GitHub","last_seen":"2026-03-17"},{"name":"VHDL","last_seen":"2026-03-17"}]},"similar_stacks":[{"name":"Mirafra Technologies","url":"https://alion.io/company/mirafra-technologies/technologies","shared_technologies":9},{"name":"Vector Atomic","url":"https://alion.io/company/vectoratomic/technologies","shared_technologies":11},{"name":"MBRYONICS","url":"https://alion.io/company/mbryonics/technologies","shared_technologies":11},{"name":"Maxlinear","url":"https://alion.io/company/maxlinear/technologies","shared_technologies":10},{"name":"Dolphin Semiconductor","url":"https://alion.io/company/dolphin-semiconductor/technologies","shared_technologies":8},{"name":"Omni Design Technologies","url":"https://alion.io/company/omni-design-technologies","shared_technologies":10},{"name":"Lightmatter","url":"https://alion.io/company/lightmatter-co/technologies","shared_technologies":13},{"name":"Nuvoton Technology","url":"https://alion.io/company/nuvoton-technology/technologies","shared_technologies":9}],"html_url":"https://alion.io/company/celerocommunications/technologies","json_url":"https://alion.io/company/celerocommunications/technologies.json","license":"CC BY-SA 4.0","meta":{"source":"Alion","built_at":"2026-10-03T05:56:17Z","generated_at":"2026-10-03T07:55:01Z"}}