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Find and compare semiconductor IP cores for ASIC and SoC design. Browse IP vendors, categories, PHYs, controllers, memory IP, security IP, chiplet IP and analog IP.
News
CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace
The authors present CTTE (CEDARtools.TraceEncoder), an open SystemVerilog encoder with a protocol-agnostic front end and selectable N-Trace/Nexus or E-Trace back ends. CTTE implements the N-Trace 1.0 program-trace message set in both instruction-trace mod
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Perceptia Releases Design Kit for pPLL03 on Samsung Foundry 14LPU Platform
Perceptia Devices, a leader in high-performance clocking IP, today announced the availability of the design kit for its pPLL03 phase-locked loop IP on Samsung Foundry's 14LPU technology node. Published by Semi IP Hub: Perceptia Releases Design Kit for pPL
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TSMC 2nm 1V2 GPIO
This TSMC 2nm 1.2V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm and can be ported to other technologies upon r… View the complete IP profile: TSMC 2nm 1V2 GPIO
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A Resource-Efficient CNN-Based EEG Auditory Attention Decoding ASIC
This paper presents a resource-efficient ASIC for real-time EEG-based auditory attention decoding by integrating a quantized CNN inference engine and a Pearson-correlation classifier. Published by Semi IP Hub: A Resource-Efficient CNN-Based EEG Auditory A
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Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
The 12-bit, 125Msps SAR ADC IPs deliver an ENOB 10.5 bit, SFDR 82.5 dB, and THD -77.2 dB. Featuring a differential input design with high common-mode rejection ratio (CMRR), the IPs achieve an excellent anti-interference performance, enabling precise capt
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