{"id":2429435,"url":"https://alion.io/job/4staffing-lead-asic-rtl-design-engineer","title":"Lead ASIC RTL Design Engineer","company":{"id":4423782,"name":"4 Staffing Corp","domain":"4staffing.net","url":"https://alion.io/company/4staffing","size_band":"1001-5000","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Manatal","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Francisco, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":170000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-10-13T08:30:53Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-14T23:58:15Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Lead ASIC RTL Design Engineer - Remote (U.S.) - No visa sponsorship\nRole Summary\nOur client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.\nCore Responsibilities\nArchitecture & RTL Development\nDefine microarchitecture for complex subsystems and document design specifications\n\nImplement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent\n\nIncorporate assertions and design-for-debug features within RTL\n\nDesign Ownership & Implementation\nLead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness\n\nCollaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs\n\nTake responsibility for achieving performance, power, and area (PPA) targets for assigned blocks\n\nHigh-Speed Interfaces & Memory Systems\nDesign and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)\n\nWork on memory subsystem integration, including external DRAM and high-throughput memory solutions\n\nCoordinate with internal teams and third-party IP providers to ensure proper integration and functionality\n\nEngineering Processes & Tooling\nEstablish and maintain RTL design standards, reusable components, and signoff criteria\n\nContribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)\n\nCollaboration & System Integration\nPartner with verification teams on test planning, coverage goals, and model alignment\n\nWork with architecture and performance engineering to validate design intent against system-level expectations\n\nSupport silicon bring-up, debugging, and downstream customer or system integration efforts\n\nTechnical Leadership\nMentor less experienced engineers and provide guidance on design best practices\n\nLead design reviews and help drive key technical decisions across teams\n\nAdvocate for scalable, efficient, and high-quality engineering solutions\n\nBasic Qualifications\nBachelor's or Master's degree in Electrical or Computer Engineering (or similar field)\n\n8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices\n\nDemonstrated experience delivering designs from concept through RTL implementation and tape out readiness\n\nStrong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations\n\nHands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)\n\nFamiliarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths\n\nStrong communication skills with the ability to lead technical discussions and document designs clearly\n\nPreferred Experience\nExposure to AI/ML hardware or high-performance compute architectures\n\nKnowledge of formal verification techniques and assertion-based design\n\nExperience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)\n\nFamiliarity working alongside verification environments (UVM, Python-based frameworks, or similar)\n\nUnderstanding of modern processor subsystems, coherence models, or custom tool flows","description_format":"text","description_chars":3590,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-13T08:30:53Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":29,"reasons":["conf:2","win:early"],"computed_at":"2026-10-14T06:34:16Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/4staffing-lead-asic-rtl-design-engineer","json_url":"https://alion.io/job/4staffing-lead-asic-rtl-design-engineer.json","meta":{"generated_at":"2026-10-15T01:57:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per 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