Senior RTL Integration Engineer
First seen by Alion on Sep 22, 2026.
Job Description :
We are seeking a high-calibre RTL Integration Engineer with 7+ years of experience to lead SoC and subsystem integration for next-generation semiconductor products. You will be responsible for integrating complex internal/third-party IPs, managing bus fabrics, running static quality checks, and collaborating with cross-functional teams to ensure high-quality design handoffs.
Responsibilities :
- Integrate multi-million gate SoCs, sub-systems, and third-party IPs (e. g., PCIe, DDR, Ethernet, ARM/RISC-V cores) using SystemVerilog and Verilog.
- Configure and assemble chip interconnect fabrics using AMBA bus protocols (AXI, AHB, APB, CHI).
- Own and execute static verification flows, including Linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and UPF-based low-power intent checks (using tools like SpyGlass, Questa CDC, or VC-SpyGlass).
- Develop and maintain top-level timing constraints (SDC) and work closely with Physical Design (PD) and Synthesis teams to resolve timing, area, and power issues.
- Drive functional and timing ECOs late in the execution cycle.
- Build, maintain, and optimise RTL build systems and automated integration flows using Python, TCL, Perl, or Shell scripting.
- Mentor junior engineers and collaborate with Verification, DFT, and Architecture teams to define integration specs and debug full-chip issues.
Requirements :
- Education : B. E. /B. Tech/M. E. /M. Tech in Electrical/Electronics Engineering, VLSI, or related disciplines.
- Experience : 7+ years of hands-on experience in SoC/Subsystem RTL integration within the VLSI/Semiconductor industry.
Core Technical Expertise :
- Advanced knowledge of SystemVerilog/Verilog and digital design principles.
- In-depth understanding of AMBA protocols (AXI4 AHB, APB, CHI) and memory controller/interconnect architecture.
- Proven track record running static sign-off checks (Lint, CDC, RDC, UPF/CPF low-power intent).
- Solid understanding of logical synthesis, SDC timing constraints, and physical design interfaces.
- Automation: Strong proficiency in scripting using Python, TCL, or Perl for workflow automation.
- Key Attributes: Strong diagnostic and problem-solving skills, with a track record of driving complex designs through tapeout.
Skills
RTL, SoC, Verilog, AMBA, Clock Domain Crossing, Linting, Python, TCL, Synthesis, Verification