{"id":681586,"url":"https://alion.io/job/accelercomm-senior-hardware-design-engineers","title":"Senior Hardware Design Engineers","company":{"id":669490,"name":"Accelercomm","domain":"accelercomm.com","url":"https://alion.io/company/accelercomm","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Pinpoint","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":true,"relocation_package":false,"has_equity":true,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Agile","optional":true},{"name":"C++","optional":true},{"name":"Python","optional":true},{"name":"SystemC","optional":true},{"name":"UVM","optional":true},{"name":"Waterfall","optional":true}],"status":"live","first_seen_at":"2026-09-09T23:36:43Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-11-01T20:10:34Z","board_verified":true,"closed_at":null,"days_open":52,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":52},"description":"We are looking for multiple Senior Design Engineers, at all levels from Senior Engineer to Senior Principal Engineer. You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.\nYou will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.\n\nAccelerComm will NOT sponsor H1 visa nor practical training.\nKey Responsibilities\nAs a Senior Hardware Design Engineer, you will be responsible for:\nDesigning micro-architectures and RTL implementations to meet the requirements provided by Algorithm and System Architecture teams. Providing feedback to Algorithm and System Architecture teams to improve efficiency of RTL designs\nImplementing designs targeting FPGA and/or ASIC using industry standard techniques, design flows and tools, including the creation of appropriate block level and system level testbenches\n\nDeploying your designs onto the latest FPGA development platforms for validation and system integration\n\nActively engaging with and adhering to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product\nSkills, Knowledge and Expertise\n\nEssential:\nExpert knowledge of Verilog and SystemVerilog for complex ASIC/FPGA products\nMinimum 5 years of experience in industry, designing and delivering successful FPGA/ASIC designs implementing multiple Gbps high-speed data communication and connectivity protocols or baseband processing\nA strong skillset in delivering digital designs in the ASIC and FPGA industry \nA strong work ethic and focus on completing designs on time to meet customer delivery schedules\nOptimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis\nTrack record in collaborating across teams to produce integrated solutions \nExperience in technical documentation writing - design specifications, user guides, verification plans\nExpert user of EDA tools for simulation and synthesis\n Desirable:\nKnowledge of 3GPP L1 and digital communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) \nFamiliarity with the AMBA/AXI bus protocols\nUnderstanding of UVM verification techniques or practical experience using UVM for IP verification\nExperience using C++/SystemC for design modelling and integration \n Experience with high speed interfaces such as PCI-E or JESD\nKnowledge of a scripting language, such as Python\nKnowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability\nExperience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools\nBenefits\nWe offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to stock options and a range of good quality company benefits including 401K, health/dental/optical insurance. We operate flexible working hours and offer hybrid working.","description_format":"text","description_chars":3499,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["401k plan","Flexible schedule","Hybrid work","Stock options"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Mobile Networks","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-10T23:36:43Z"}],"visa":[],"liveness":{"score":15,"band":"cold","label":"Long shot","p_open":1,"p_active":0.425,"p_room":0.35,"age_days":52,"expected_fill_days":12,"reasons":["conf:2","velocity","win:tail"],"computed_at":"2026-11-01T06:10:25Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/accelercomm-senior-hardware-design-engineers","json_url":"https://alion.io/job/accelercomm-senior-hardware-design-engineers.json","meta":{"generated_at":"2026-11-01T22:32:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":34331,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":669490},"rest":"https://alion.io/mcp/rest/get_company?id=669490"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faccelercomm-senior-hardware-design-engineers"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faccelercomm-senior-hardware-design-engineers"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faccelercomm-senior-hardware-design-engineers"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/accelercomm-senior-hardware-design-engineers\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faccelercomm-senior-hardware-design-engineers"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":681586}},{"tool":"search_jobs","arguments":{"company":"accelercomm.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":681586},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}