{"id":2791134,"url":"https://alion.io/job/accelercomm-senior-verification-engineer-4","title":"Senior Verification Engineer","company":{"id":669490,"name":"Accelercomm","domain":"accelercomm.com","url":"https://alion.io/company/accelercomm","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Pinpoint","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":121000,"max_usd":220000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1396},"experience_years_min":3,"visa_sponsorship":true,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Bash","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"MATLAB","optional":true}],"status":"live","first_seen_at":"2026-10-16T19:50:18Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T13:08:05Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP.\nKey Responsibilities\nResponsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.\n Develop verification plans from design and architecture specifications. \nCreate and maintain SystemVerilog/UVM verification environments. \nDevelop testbenches, assertions, scoreboards and coverage models. \nExecute directed and constrained-random verification. \nAnalyse coverage and debug RTL and verification issues. \nSupport subsystem and system-level integration activities. \nContribute to automation, regression and CI workflows. \nParticipate in design reviews and verification sign-off. \nMentor and support junior colleagues\nSkills, Knowledge & Expertise\n\nRequired\nDegree in Electronic Engineering, Computer Engineering or a related discipline. \nAt least 3 years experience verifying digital ASIC and/or FPGA designs. \nStrong SystemVerilog and UVM skills. \nUnderstanding of RTL design principles and hardware implementation. \nExperience with coverage-driven and assertion-based verification. \nLinux proficiency and scripting skills (Python, Tcl or Bash). \nStrong analytical, debugging and problem-solving skills. \nExperience using AI to accelerate verification without sacrificing quality \nAbility to work across multiple teams\n\nDesirable\nExperience in 4G/5G, NTN, satellite communications or DSP systems. \nKnowledge of modem architectures and Layer 1 processing. \nExperience with Formal Verification, FPGA prototyping and CI environments. \nFamiliarity with MATLAB or equivalent modelling tools. \nJob Benefits\nWe offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to stock options and a range of good quality company benefits including 401K, health/dental/optical insurance. We operate flexible working hours and offer hybrid working.\nApplicants with existing H-1B visa or practical training work authorization are welcome to apply if they are seeking a change of employer. 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