Senior FPGA Engineer (VHDL/Verilog)
AGAD Technology
As a Senior FPGA Engineer, you will contribute to the development of key components of our networking system, including SmartNICs and hybrid optical switches. You will be responsible for designing and optimizing VHDL and/or Verilog implementations. In the next phase, you will verify your designs in simulation by writing test cases and scenarioʼs within our Python simulation environment. You will integrate your designs and IP cores into our FPGA projects. Next to this, timing analysis and on-target verification are key responsibilities of this role.
Finally, you will participate in the system level performance testing and debug fixing in close collaboration with the software and networking team.
Requirements
Must-have
- Masterʼs degree in electronics engineering, or similar by experience.
- Strong knowledge of VHDL and Verilog development. Programming skills in Tcl and Python.
- Experience in timing analysis and closure.
- Experience with unit simulation testing and test automation (Jenkins).
- Familiar with working in a Linux environment. Understanding of networking concepts (Ethernet, TCP/IP, MAC addressing, buffering, etc.).
- Strong problem-solving and debugging skills. Eagerness to familiarize yourself with new and cutting-edge technologies.
Nice-to-have
- Familiar with Xilinx FPGA tools and QuestaSim/ModelSim.
- Experience working with Cocotb verification environment.
- Knowledge of high-speed interfaces: DDR4, Ethernet, PCIe, AXI4, AXI-lite.
The working mode is hybrid. Consultants must be based close to the client's premises.