{"id":1319844,"url":"https://alion.io/job/akeana-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":1952628,"name":"Akeana","domain":"akeana.com","url":"https://alion.io/company/akeana","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Schema","truth_index":{"grade":"B","score":75,"open_postings":6,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2022-07-18T11:23:42Z","employer_posted_date":"2024-03-05","last_verified_at":"2026-09-30T07:15:24Z","board_verified":true,"closed_at":null,"days_open":1535,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":1535},"description":"Senior Design Verification Engineer\n\nJoin and be part of an exciting startup in the semiconductor space!\n\nWe are a well-funded early-stage startup doing processor design.\nThe company was founded by industry veterans from Broadcom/Marvell/Sun Microsystems/Intel, who have taken multiple successful high-performance CPUs to tape-out and production.\nIf you have a strong background in processors, great problem-solving skills, an eye for detail, and a can- do attitude, reach out to us, to explore opportunities.\n\nFor this position, we are looking for:\n\nStrong background in unit/cluster-level verification, of a complex CPU or Cache Coherent sub- system\n\nProcessor architecture (such RiscV, ARM, Mips, Solaris, x86) or Cache coherency experience, and experience in previous processor verification is a plus.\n\nStrong programming background in System Verilog or C++. UVM experience desirable.\n\nGood knowledge of assembly or C-programming a plus\n\nYou will be working with a small close-knit team and own 1 or more areas of verification.\nAs a DV engineer you will also be interacting with Architecture, and RTL design closely.\nThis is a great opportunity to join an early-stage startup and work on exciting designs with significant responsibility.","description_format":"text","description_chars":1241,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Hardware","Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-26T21:02:42Z"}],"liveness":{"score":5,"band":"cold","label":"Long shot","p_open":1,"p_active":0.19,"p_room":0.28,"age_days":1535,"expected_fill_days":24,"reasons":["conf:22","win:tail","crowd:"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/akeana-senior-design-verification-engineer","json_url":"https://alion.io/job/akeana-senior-design-verification-engineer.json","meta":{"generated_at":"2026-10-01T09:52:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":701,"day_limit":5000,"remaining_today":4299,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}