{"id":723861,"url":"https://alion.io/job/alifsemi-sr-digital-implementation-engineer","title":"Sr. Digital Implementation Engineer","company":{"id":669281,"name":"alifsemi","domain":"alifsemi.com","url":"https://alion.io/company/alifsemi","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"D","score":40,"open_postings":10,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Solutions","role_family":"Solutions","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":122000,"max_usd":244000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1026},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Tessent","optional":false},{"name":"Verilog","optional":false},{"name":"Synopsys Design Compiler","optional":true}],"status":"live","first_seen_at":"2022-11-09T16:27:45Z","employer_posted_date":"2022-11-09","last_verified_at":"2026-10-31T14:07:47Z","board_verified":true,"closed_at":null,"days_open":1452,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":1451},"description":"You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).\nAdditional Responsibilities\nRun complete synthesis flow \nDefine and document synthesis (including DFT insertion) methodology and scripts/flows \nUPF flow for defining power intent (at block and chip level) \nRTL and Netlist hand-off checks (LEC) \nInterface with Physical Design for floor-planning and timing closure \nAssist with design partitioning and floorplan. \nAnalyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teams\nRequired Qualifications\nSignificant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure \nFamiliarity with DFT (Tessent) and back-end (Cadence) tools Hands-on experience with digital logic synthesis for power and area optimization \nExperience in low power design issues, tools, and methodology including UPF power intent specification \nProficient in Verilog/SV/Tcl/Perl/Python \nHighly motivated to debug and resolve CAD tool flow issues \nSelf-starter with good analytical, problem solving and communication skills \nBachelor’s degree in Electrical Engineering, a related discipline, or equivalent experience.\nPreferred Qualifications\nStrong expertise with Design Compiler or Genus. \nExperience with IP integration \nExperience with Synthesis, LEC, DFT, BIST \nExperience with Cadence Timing and ECO Flow \nExperience with Clock Domain Crossing (CDC) Analysis \nExperience with timing corner selection and library models \nProven track record of successful deep submicron technology node tapeout (including Silicon bring-up) \nDetailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, 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