{"id":4229856,"url":"https://alion.io/job/allegro-microsystems-memory-design-engineer-2","title":"Memory Design Engineer","company":{"id":2040619,"name":"Allegro MicroSystems","domain":"allegromicro.com","url":"https://alion.io/company/allegromicro-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":11,"ghost_share":0,"stale_share":0.909,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Milan, Italy"],"countries":["IT"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Cadence Quantus","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-12T00:00:00Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-14T16:37:11Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"The Allegro team is united by a clear purpose-advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business-from breakthrough product development and customer success to how we show up for each other and the communities we serve.\nAbout the Department\nThe Technology Development group is an integral organization of Allegro that includes Device Development, Foundry Operations, Modeling, ESD/EMC, and Design Enablement teams. The group facilitates all semiconductor devices and design automation research and development programs from concept through maturity. We ensure that the technology roadmap is aligned with the product roadmap and work across organizations. We manage partnerships with external foundries and suppliers to deliver cutting-edge semiconductor devices and design automation tools to support the product roadmap.\nThe Opportunity\nThe Memory Design Engineer will report to the Director of Design Enablement and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in EDA software environment for semiconductor technology development and device modeling. In addition, this role will support the release of Foundry mask manufacturing requirements for a global design community. Candidate will design and verify standard IP memories that include Single-Port SRAM, Register File, ROM, One-Time-Programmable, EEPROM, and FLASH. This work directly impacts the development of our BCD technology and the success of our global design community.\nWhat You Will Do\nDesign NVM, VM, driver circuit, and digital IP.\nIP in silicon test and validation.\nCoordinate design requirements, macro floor planning, and layout design.\nCharacterization and standardization of memory/digital IP for global design use within a custom PDK environment.\nDocumentation development and publishing of IP specifications and application use cases.\nWhat You Will Need\nA qualified candidate for a Senior role requires a BSEE with +4 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.\nNew Graduate Opportunity: We are also open to evaluating highly motivated New Graduate candidates who possess a strong academic background, excellent theoretical knowledge, and a passionate interest in integrated circuit design.\nApplications knowledge of the following is required:\nDigital components (logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data communication protocols, microprocessors and microcontrollers).\nAbility to develop Memory test/validation plans.\nAbility to characterize Memory/Standard Cells in standard liberty format.\nAbility to work with design teams on memory debug and diagnostics.\nEDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Quantus/Calibre) and IP Characterization tools.\nSW Experience includes the basic understanding of HDL languages (Verilog, VerilogA, and VerilogAMS). Skill, C, and SystemVerilog are a plus.\nExperience with layout parasitic/leakage design trade-offs.\nSolid understanding of modeling challenges for sub-micron technologies.\nUnderstanding of device physics at the transistor design level (cross section, STI, DTI) is preferred.\nOur Total Rewards package is designed based on objective, job-based criteria, tailored to the local labor market where the work is performed. Our team will discuss with you the specifics of our comprehensive package intended to support the diverse needs of our employees. Base salary is an important component of our Total Rewards package. The base salary range for this position is between 36.000 and 60.000. Actual starting pay will be carefully determined based on relevant experience, qualifications, specialized skills, localized market conditions, and internal equity.\nWhy Allegro?\nJoin Allegro and become part of a team where your contributions truly matter.\nWe foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.\nYour work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.\nYou’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.\nJoin us-and help build what’s next.","description_format":"text","description_chars":4597,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Sensors & Transducers","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-11-13T09:22:51Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":34,"reasons":["conf:1","stale_co","velocity","win:early"],"computed_at":"2026-11-14T05:58:10Z"},"pay":null,"html_url":"https://alion.io/job/allegro-microsystems-memory-design-engineer-2","json_url":"https://alion.io/job/allegro-microsystems-memory-design-engineer-2.json","meta":{"generated_at":"2026-11-14T17:06:18Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19666,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2040619},"rest":"https://alion.io/mcp/rest/get_company?id=2040619"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fallegro-microsystems-memory-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fallegro-microsystems-memory-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fallegro-microsystems-memory-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/allegro-microsystems-memory-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fallegro-microsystems-memory-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4229856}},{"tool":"search_jobs","arguments":{"company":"allegromicro.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4229856},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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