{"id":1558600,"url":"https://alion.io/job/allegro-microsystems-mixed-signal-design-verification-engineer-3","title":"Mixed Signal Design Verification Engineer","company":{"id":2040619,"name":"Allegro MicroSystems","domain":"allegromicro.com","url":"https://alion.io/company/allegromicro-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":78,"open_postings":10,"ghost_share":0,"stale_share":0.9,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Manchester, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":74000,"max_usd":145000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":468},"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bash","optional":false},{"name":"Cadence Allegro","optional":false},{"name":"Cadence AMS Designer","optional":false},{"name":"GitLab","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-20T00:00:00Z","employer_posted_date":"2026-09-20","last_verified_at":"2026-10-19T11:15:38Z","board_verified":true,"closed_at":null,"days_open":30,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":30},"description":"The Allegro team is united by a clear purpose-advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business-from breakthrough product development and customer success to how we show up for each other and the communities we serve.\nThe Opportunity\nAllegro MicroSystems is seeking an enthusiastic and motivated Mixed-Signal Design Verification (MSDV) Engineer to join our development team. In this role, you will work under the guidance of senior technical leads to develop and execute top-level mixed-signal verification testbenches for our market-leading automotive and industrial integrated circuits. You will act as a key interface between transistor-level analog building blocks and digital control systems, running functional simulations across power sequencing, register configurations, and system-level testcases to ensure first-pass silicon success.\nWhat You Will Do\nRun and debug top-level AMS simulations using Cadence AMS Designer and Virtuoso to verify chip-level interactions between analog front-ends and digital logic.\nAssist in writing and maintaining behavioral models and testbenches using Verilog, SystemVerilog, and Verilog-AMS/Real-Number Modeling (RNM/wreal).\nVerify power-up/power-down sequences, brown-out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners to ensure proper start-up behavior.\nValidate register maps, EEPROM configuration loads, read/write protocols, and trim test modes against design specifications.\nLog and track verification bugs using GitLab issue tracking, applying standard workflow states (Analysis Pending, Verified) to support tapeout readiness.\nPartner with Analog Design, Digital Design, and Systems Engineering to review coverage metrics in Jama Connect and support testcase closure.\nWhat You Will Bring\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.\n1-3 years of industry or relevant academic/internship experience in mixed-signal design verification or IC design.\nFamiliarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).\nUnderstanding of HDL languages (Verilog, SystemVerilog) and introductory knowledge of Verilog-A/AMS.\nSolid grasp of fundamental analog circuits (amplifiers, bandgaps, LDOs, ADCs, oscillators) and digital logic basics.\nBasic familiarity with Linux environments and scripting (Python, Bash, or Skill) is a plus.\nExposure to issue-tracking tools (e.g., GitLab) and requirements management systems (e.g., Jama Connect).\nCurious, proactive problem-solver with strong written and verbal communication skills who enjoys learning and collaborating in a global engineering environment.\nWhy Allegro?\nJoin Allegro and become part of a team where your contributions truly matter.\nWe foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.\nYour work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.\nYou’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.\nJoin us-and help build what’s next.\nAt Allegro, we are committed to providing a harassment-free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status, parental status, or any other basis covered by appropriate law. Allegro makes hiring decisions based solely on qualifications, merit, and business needs at the time.\nEligible applicants must reside in a state where Allegro currently has an office location: This includes New Hampshire, Massachusetts, Texas, and Michigan. Certain positions (such as field sales roles) may be exempt from this requirement.","description_format":"text","description_chars":4151,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"Texas","iso":null,"kind":"city"},{"name":"Michigan","iso":null,"kind":"city"},{"name":"Massachusetts","iso":null,"kind":"city"},{"name":"New Hampshire","iso":null,"kind":"city"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Industrial Automation","Motors, Drives & Motion Control"],"lifecycle":[{"event":"open","at":"2026-10-01T03:11:37Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 15 · green card filings: 1","filings_12m":15,"filings_prev_12m":20,"green_card_filings_12m":1,"median_offered_wage_usd":125625,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":12}],"liveness":{"score":38,"band":"fade","label":"Fading","p_open":1,"p_active":0.508,"p_room":0.75,"age_days":29,"expected_fill_days":34,"reasons":["conf:12","stale_co","wave","velocity","win:late","comp:junior"],"computed_at":"2026-10-19T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/allegro-microsystems-mixed-signal-design-verification-engineer-3","json_url":"https://alion.io/job/allegro-microsystems-mixed-signal-design-verification-engineer-3.json","meta":{"generated_at":"2026-10-20T02:53:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3188,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2040619},"rest":"https://alion.io/mcp/rest/get_company?id=2040619"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fallegro-microsystems-mixed-signal-design-verification-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fallegro-microsystems-mixed-signal-design-verification-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fallegro-microsystems-mixed-signal-design-verification-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/allegro-microsystems-mixed-signal-design-verification-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fallegro-microsystems-mixed-signal-design-verification-engineer-3"}]}