{"id":1558626,"url":"https://alion.io/job/allegro-microsystems-principal-digital-design-engineer","title":"Principal Digital Design Engineer","company":{"id":2040619,"name":"Allegro MicroSystems","domain":"allegromicro.com","url":"https://alion.io/company/allegromicro-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":78,"open_postings":10,"ghost_share":0,"stale_share":0.9,"repost_share":0,"time_to_fill_p50_days":37,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-02T00:00:00Z","employer_posted_date":"2026-09-02","last_verified_at":"2026-10-14T15:12:25Z","board_verified":true,"closed_at":null,"days_open":43,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":43},"description":"The Allegro team is united by a clear purpose-advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business-from breakthrough product development and customer success to how we show up for each other and the communities we serve.\nROLE OVERVIEW\nIn this position, you will be a technical leader within a multi-site, growing, and dynamic team, defining and driving the digital architecture for our industry-leading mixed-signal motor drive ICs. You will be responsible for leading the architecture, design, and verification strategy for a wide range of complex digital solutions, from standalone IP to full System-on-Chip (SoC) designs. This role will provide you with the opportunity to influence the technical direction and solve the most challenging problems in automotive motor control.\nRESPONSIBILITIES\nLead the definition of system-level requirements and own the digital architecture for complex digital solutions, including both IP-level and full SoC architectures.\n\nArchitect and lead the implementation of complex, reusable RTL modules and top-level chip integration using Verilog, ensuring adherence to best practices for low-power and high-performance design.\n\nOwn and drive the evolution of the digital design methodology, identifying, evaluating, and deploying new tools and best practices to enhance efficiency and quality.\n\nOversee the FPGA validation and pre-silicon emulation strategy, ensuring robust verification of the entire system and seamless interface between hardware and software.\n\nSupport the overall verification strategy in collaboration with the verification team, defining success criteria, and ensuring comprehensive functional coverage to deliver first-pass silicon success.\n\nCollaborate with the physical implementation team to resolve critical timing, power, and area challenges on advanced technology nodes.\n\nMentor junior and senior engineers, fostering technical growth and excellence within the digital design team.\n\nKEY RELATIONSHIPS\nInternal\nAct as a technical authority, collaborating with and guiding digital design and verification engineers.\n\nServe as the primary technical interface to the physical implementation, systems, software, and applications teams.\n\nPartner with systems engineers and marketing to define next-generation product requirements and technical roadmaps.\n\nProvide expert guidance to test engineers on the development of robust ATPG and production test programs.\n\nExternal\nLead technical discussions with key customers and off-site design teams.\n\nDrive technical engagements with EDA and IP vendors to influence their roadmaps and resolve critical issues.\n\nPERSON SPECIFICATION\nQualifications\nEssential: Prospective candidates must have a PhD or Master's degree (or equivalent) in Electronics or a related field, combined with extensive, proven experience in a senior or principal digital design role.\n\nSkills, Knowledge, and Aptitudes\nEssential:\nExpert-level knowledge of digital architectures, ranging from complex algorithmic IP to full SoC designs including CPU subsystems, interconnect fabrics (e.g., AMBA/AXI), and system-level protocols.\n\nProven track record of leading complex digital architecture and integration (IP and/or SoC), from specification through to tape-out and silicon validation.\n\nMastery of advanced digital design principles, including low-power and high-speed design techniques.\n\nDeep understanding and practical application of advanced DFT/DFM techniques, including scan compression, boundary scan, and memory BIST.\n\nExpertise in advanced FPGA prototyping and emulation techniques for complex digital systems.\n\nRecognized technical leader with the ability to influence and guide cross-functional teams and make critical technical trade-offs.\n\nDemonstrated ability to mentor and develop other engineers.\n\nExceptional verbal and written communication skills, with the ability to present complex technical concepts to a wide range of audiences.\n\nDesirable:\nExpertise with Cadence or equivalent EDA toolsets for the entire front-end design and verification flow.\n\nExperience with functional safety standards such as ISO 26262.\n\nTRAVEL REQUIREMENTS\nDomestic and international travel may be required for this role. The below provides an indication only of the amount, type, and locations of travel. This is subject to change depending on business requirements.\nNational Travel: 5-10%\n\nInternational Travel: 5-10%\n\nTravel Locations: Dependent on work that may arise, most likely travel will be within Europe, the Americas, and Asia.\n\nWhy Allegro?\nJoin Allegro and become part of a team where your contributions truly matter.\nWe foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.\nYour work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.\nYou’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.\nJoin us-and help build what’s next.","description_format":"text","description_chars":5225,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Industrial Automation","Motors, Drives & Motion Control"],"lifecycle":[{"event":"open","at":"2026-10-01T03:11:37Z"}],"visa":[],"liveness":{"score":30,"band":"fade","label":"Fading","p_open":1,"p_active":0.542,"p_room":0.55,"age_days":43,"expected_fill_days":37,"reasons":["conf:14","stale_co","velocity","win:tail"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/allegro-microsystems-principal-digital-design-engineer","json_url":"https://alion.io/job/allegro-microsystems-principal-digital-design-engineer.json","meta":{"generated_at":"2026-10-15T07:58:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12103,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2040619},"rest":"https://alion.io/mcp/rest/get_company?id=2040619"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fallegro-microsystems-principal-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fallegro-microsystems-principal-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fallegro-microsystems-principal-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/allegro-microsystems-principal-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fallegro-microsystems-principal-digital-design-engineer"}]}