{"id":1753140,"url":"https://alion.io/job/allegro-microsystems-senior-digital-verification-engineer","title":"Senior Digital Verification Engineer","company":{"id":2040619,"name":"Allegro MicroSystems","domain":"allegromicro.com","url":"https://alion.io/company/allegromicro-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":10,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-04T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Prague, Czech Republic"],"countries":["CZ"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":51000,"max_usd":117000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1198},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"CI/CD","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Formal Verification","optional":true},{"name":"Git","optional":true}],"status":"live","first_seen_at":"2026-10-02T00:00:00Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-05T01:42:30Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"The Allegro team is united by a clear purpose-advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business-from breakthrough product development and customer success to how we show up for each other and the communities we serve.\nAbout the Role \nAllegro MicroSystems is seeking a Digital Verification Engineer to join our team developing next-generation magnetic position/current sensors, motor drivers, and power management ICs. You will be responsible for verifying complex digital and mixed-signal designs, ensuring first-pass silicon success for products that drive e-mobility, clean energy, automation, and robotics forward.\nKey Responsibilities\nDevelop and execute verification plans for digital and mixed-signal IP and full-chip designs.\nBuild and maintain constrained-random, coverage-driven testbenches using SystemVerilog and UVM.\nDefine functional coverage, assertions (SVA), and checkers to measure and close verification goals.\nPerform block-level, subsystem, and top-level (full-chip) verification, including analog/digital interaction using Verilog-AMS / real-number modeling.\nDebug failures in collaboration with RTL designers, analog designers, and firmware teams.\nContribute to regression setup, automation, and continuous-integration verification flows.\nTrack and report coverage closure, bug metrics, and sign-off readiness.\nParticipate in design and verification reviews.\nRequired Qualifications\nBachelor's or Master's degree in Electrical/Electronics/Computer Engineering (or equivalent).\nStrong proficiency in SystemVerilog and the UVM methodology.\nSolid understanding of digital design fundamentals, RTL (Verilog/VHDL), and synthesis concepts.\nExperience with constrained-random, coverage-driven verification and assertion-based verification (SVA).\nProficiency with industry simulation/debug tools (e.g., Cadence Xcelium/SimVision, Synopsys VCS/Verdi, or equivalent).\nScripting skills (Python, Perl, Tcl, or shell) for automation and flow development.\nStrong problem-solving, debugging, and communication skills.\nPreferred / Nice-to-Have\nExperience with mixed-signal verification (Verilog-AMS, real-number modeling / wreal).\nFamiliarity with functional safety (ISO 26262) and/or automotive quality (AEC-Q100) requirements.\nExposure to formal verification methods and tools.\nExperience with low-power verification (UPF/CPF).\nKnowledge of sensor, motor driver, or power management IC architectures.\nExperience with version control (Git) and CI/CD for verification regressions.\nWhy Allegro?\nJoin Allegro and become part of a team where your contributions truly matter.\nWe foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.\nYour work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.\nYou’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.\nJoin us-and help build what’s next.","description_format":"text","description_chars":3209,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Industrial Automation","Motors, Drives & Motion Control"],"lifecycle":[{"event":"open","at":"2026-10-03T09:35:28Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":30,"reasons":["conf:1","stale_co","velocity","win:early"],"computed_at":"2026-10-04T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/allegro-microsystems-senior-digital-verification-engineer","json_url":"https://alion.io/job/allegro-microsystems-senior-digital-verification-engineer.json","meta":{"generated_at":"2026-10-05T02:08:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2850,"day_limit":5000,"remaining_today":2150,"minute_limit":60,"resets_at":"2026-10-06T00:00:00Z"}}}