{"id":1558647,"url":"https://alion.io/job/allegro-microsystems-technology-layout-engineer","title":"Technology Layout Engineer","company":{"id":2040619,"name":"Allegro MicroSystems","domain":"allegromicro.com","url":"https://alion.io/company/allegromicro-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":10,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-05T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Buenos Aires, Argentina"],"countries":["AR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":32000,"max_usd":76000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":524},"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false}],"status":"live","first_seen_at":"2026-06-23T00:00:00Z","employer_posted_date":"2026-06-23","last_verified_at":"2026-10-05T22:37:20Z","board_verified":true,"closed_at":null,"days_open":105,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":104},"description":"The Allegro team is united by a clear purpose-advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business-from breakthrough product development and customer success to how we show up for each other and the communities we serve.\nAbout the Department\nThe Technology Development group is an integral organization of Allegro that includes Device Development, Foundry Operations, Modeling, ESD/EMC, and Design Enablement teams. The group facilitates all semiconductor devices and design automation research and development programs from concept through maturity. We ensure that the technology roadmap is aligned with the product roadmap and work across organizations. We manage partnerships with external foundries and suppliers to deliver cutting-edge semiconductor devices and design automation tools to support the product roadmap.\nThe Opportunity\nThe Device Layout and Mask Tooling Engineer will report to the Principal Design Enablement Engineer and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in EDA software environment for semiconductor technology development and device modeling. In addition, this role will support the release of Foundry mask manufacturing requirements for a global design community. Candidate is responsible for developing and supporting internal/external mask tape out systems, generating and verifying GDS mask data, and MPW/Shuttle releases. This work directly impacts the development of our BCD technology and the success of our global design community.\nWhat You Will Do\nGenerate semiconductor component layouts in Cadence to support semiconductor technology development, process technology transfers, and device modeling.\n\nPrimary interface and support of product design MASK/GDS releases to Foundry.\n\nSupport Allegro product design Business Units with MASK tooling, Job deck review (JDV), and internal tape out system requirements.\n\nSupport Allegro product design Business Units with MASK manufacturing requirements within the Foundry standard systems.\n\nDevelop technology mask tape out workflow standards and documentation.\n\nGenerate technology mask GDS using PDK Booleans for design review and Foundry manufacturing.\n\nWhat You Will Need\nA qualified candidate requires a BSEE with a minimum of 1 year of experience in the industry.\n\nBasic understanding of EDA design software.\n\nWorking understanding of PDK components to include design rules, mask-gen, models, process parameters, test-chips, and design integration.\n\nFamiliarity with web-based design management tools, documentation, and bug tracking systems.\n\nAbility to perform in an aggressive learning and problem-solving team environment.\n\nProficiency in English is required\n\nPreferred Qualifications\nEDA software physical verification tools.\n\nKnowledge of BCD/BI-CMOS fabrication methods.\n\nFundamental understanding of device physics at the transistor design level (cross section, STI, DTI, field plating)\n\nPlease submit resumes in English for our team to review.\nWhy Allegro?\nJoin Allegro and become part of a team where your contributions truly matter.\nWe foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.\nYour work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.\nYou’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.\nJoin us-and help build what’s next.","description_format":"text","description_chars":3739,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Industrial Automation","Motors, Drives & Motion Control"],"lifecycle":[{"event":"open","at":"2026-10-01T03:11:37Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long 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