{"id":2055203,"url":"https://alion.io/job/altera-ai-architect-agentic-ai-for-chip-design-eda","title":"AI Architect, Agentic AI for Chip Design & EDA","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":90,"open_postings":17,"ghost_share":0,"stale_share":0.353,"repost_share":0.059,"time_to_fill_p50_days":57,"computed_at":"2026-10-20T05:45:00Z"}},"role":"AI/ML","role_family":"AI/ML","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":209500,"max":295000,"currency":"USD","period":"year","gross":null,"usd_annual":295000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"C++","optional":false},{"name":"Java","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"RAG","optional":false},{"name":"Reinforcement Learning","optional":false},{"name":"Spark","optional":true}],"status":"live","first_seen_at":"2026-10-07T23:32:19Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-20T18:53:46Z","board_verified":true,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"Job Details:\nJob Description:\nWe are seeking a visionary and highly technical leader to drive the next generation of AI-powered semiconductor design solutions. This role will lead the development of Agentic AI, Generative AI, and machine learning technologies that transform the end-to-end silicon development lifecycle, from architecture and RTL development through physical design, manufacturing, and yield optimization.\nThe ideal candidate combines deep semiconductor expertise with advanced AI/ML experience and has a proven track record of building innovative software platforms, automation frameworks, and AI-driven design solutions. This individual will partner closely with design engineering, EDA, manufacturing, and data science teams to accelerate productivity, improve PPA (Power, Performance, and Area), reduce design cycle times, and advance autonomous chip design capabilities.\nKey Responsibilities\nAI-Powered Chip Design & EDA Innovation\nLead the strategy, architecture, and development of AI-driven solutions for semiconductor design and optimization.\nDevelop and deploy Agentic AI systems that automate complex engineering workflows across RTL, synthesis, physical design, signoff, DRC, power planning, validation, and 3D-IC design.\nBuild intelligent multi-agent platforms capable of autonomous decision-making, design exploration, and flow optimization.\nAdvance domain-specific Large Language Models (LLMs) and foundation models tailored for semiconductor workflows.\nDrive applications leveraging Retrieval Augmented Generation (RAG), AI copilots, code generation, and autonomous engineering agents.\nSemiconductor Design Optimization\nLead AI initiatives that improve chip Power, Performance, Area (PPA), manufacturability, reliability, and silicon yield.\nDevelop machine learning and reinforcement learning solutions for automated design space exploration and optimization.\nApply Graph Neural Networks (GNNs), deep learning, and predictive analytics to accelerate semiconductor design convergence.\nPartner with product and engineering teams to integrate AI capabilities into commercial EDA platforms.\nData, Software & Infrastructure\nArchitect enterprise-scale AI and analytics platforms supporting EDA workloads and semiconductor design data.\nDevelop scalable software systems utilizing Python, C/C++, databases, cloud infrastructure, big data technologies, and distributed computing frameworks.\nCreate full-stack applications that analyze design data, identify bottlenecks, and provide actionable optimization recommendations.\nBuild and maintain large-scale data pipelines, analytics frameworks, APIs, and AI application infrastructure.\nDesign-to-Manufacturing & Silicon Intelligence\nDrive Design Technology Co-Optimization (DTCO) initiatives linking design, process development, manufacturing, and yield learning.\nDevelop AI/ML solutions for defect analysis, hotspot detection, manufacturability assessment, and yield prediction.\nLeverage silicon learning and manufacturing data to establish closed-loop optimization methodologies.\nPartner with foundry, silicon validation, and design enablement teams to improve technology development and production ramp efficiency.\nTechnical Leadership\nServe as a thought leader in AI for semiconductor design and EDA.\nLead cross-functional engineering teams and mentor senior engineers, researchers, and architects.\nInfluence product roadmaps and represent the company at industry conferences, customer engagements, and technology forums.\nDrive innovation through patents, publications, and strategic partnerships.\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$209.5K - $295.0K USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications\nPh.D. in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field.\n12+ years of semiconductor industry experience with expertise spanning multiple phases of the silicon lifecycle.\nDeep understanding of digital IC design, RTL development, synthesis, physical implementation, timing closure, verification, and signoff methodologies.\nStrong expertise in AI/ML technologies, including Generative AI, LLMs, reinforcement learning, graph neural networks, and predictive modeling.\nAdvanced programming skills in Python and one or more of C/C++, Java, or similar languages.\nExperience building enterprise software, AI platforms, analytics applications, or automation systems.\nProven technical leadership experience leading large-scale engineering initiatives.\nStrong understanding of semiconductor manufacturing, yield analysis, DTCO, or design enablement.\nPreferred Qualifications\nExperience developing Agentic AI systems for engineering or semiconductor applications.\nHands-on expertise with leading EDA tools and workflows from Cadence, Synopsys, Siemens EDA, or equivalent platforms.\nExperience developing domain-specific LLMs, RAG architectures, AI copilots, or autonomous workflow solutions.\nExpertise with cloud computing, distributed systems, Spark, data engineering, and large-scale AI infrastructure.\nKnowledge of 3D-IC, advanced packaging, silicon photonics, advanced process technologies, or foundry operations.\nTrack record of patents, publications, conference presentations, or industry-recognized technical contributions.\nExperience leading global, multidisciplinary engineering teams.\nWhat Success Looks Like\nAccelerating semiconductor design productivity through AI-driven automation.\nDelivering measurable improvements in PPA, design quality, and engineering efficiency.\nAdvancing autonomous chip design through Agentic AI and intelligent workflow orchestration.\nCreating scalable platforms that bridge semiconductor engineering, AI, and data science.\nInfluencing the future direction of AI-enabled EDA and semiconductor innovation.\nIdeal Candidate Profile\nThe successful candidate is a recognized expert at the intersection of semiconductor design, EDA, artificial intelligence, and software engineering. They possess rare end-to-end knowledge of the silicon lifecycle and a passion for building groundbreaking AI technologies that redefine how chips are designed, optimized, and brought to market.\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":7127,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-07T23:32:19Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 71","filings_12m":71,"filings_prev_12m":39,"green_card_filings_12m":0,"median_offered_wage_usd":157500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":8}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":12,"expected_fill_days":57,"reasons":["conf:29","velocity","win:early","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":{"stated_usd_annual":295000,"is_top_pay":true},"html_url":"https://alion.io/job/altera-ai-architect-agentic-ai-for-chip-design-eda","json_url":"https://alion.io/job/altera-ai-architect-agentic-ai-for-chip-design-eda.json","meta":{"generated_at":"2026-10-20T19:12:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22138,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-ai-architect-agentic-ai-for-chip-design-eda"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-ai-architect-agentic-ai-for-chip-design-eda"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-ai-architect-agentic-ai-for-chip-design-eda"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-ai-architect-agentic-ai-for-chip-design-eda\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-ai-architect-agentic-ai-for-chip-design-eda"}]}