Analog Layout Design Engineer
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Location
In office (Malaysia)
Seniority
Staff · 8+ years exp
Employment
Full-Time
Overview
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Altera is a American semiconductor company that specializes in manufacturing programmable logic devices, primary field-programmable gate arrays (FPGAs), System-on-a-Chip (SoC) FPGAs, and related design software. Originally founded in 1983, the company pioneered reconfigurable hardware before being acquired by Intel in 2015 and later re-established as an independent, standalone enterprise. Its high-performance hardware and intellectual property cores are widely used across data centers, telecommunications, automotive systems, defense, and edge AI applications.
Job Details:
Job Description:
We are seeking a highly skilled Analog Layout Design Engineer to join our dynamic team. The successful candidate will be responsible for leading the FPGA physical design and layout of complex digital, analog and mixed-signal integrated circuits (ICs), ensuring optimal performance, reliability, and manufacturability.
Key Responsibilities
Lead and execute layout design of digital. analog and mixed-signal circuit.
Collaborate closely with circuit designers to understand requirements, constraints, and performance targets.
Plan and manage layout schedules, resources, and deliverables, ensuring timely completion of projects.
Perform floorplanning, placement, and routing while optimizing for area, performance, and manufacturability.
Conduct thorough physical verification such as DRC, LVS, ERC including RV.
Drive design reviews and provide technical mentorship to junior layout engineers.
Interface with foundry partners to ensure compliance with process design rules and manufacturing best practices.
Document design methodology and maintain layout guidelines for future projects.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
8+ years of experience in analog/mixed-signal IC layout design.
Expert proficiency with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor Graphics).
Deep understanding of transistor level and analog circuit topologies and their layout sensitivities (matching, parasitics, noise, shielding, etc.).
Strong problem-solving skills and attention to detail.
Excellent communication skills and ability to work collaboratively in a cross-functional environment.
Experience mentoring and leading layout teams is a plus.
Job Type:
RegularShift:
Shift 1 (Malaysia)Primary Location:
Penang 15, Penang, MalaysiaAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Free account
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