CPU Design Verification Engineer
Confirmed on the employer's own hiring board on Oct 16, 2026. First seen by Alion on Jun 9, 2026. Altera scores A on the Alion truth index.
Job Details:
Job Description:
As a CPU Design Verification Engineer, you'll play a pivotal role in ensuring the functional correctness and performance of Altera's RISC-V processor family. Working alongside world-class CPU architects, RTL designers, and system design teams, you'll help validate designs that meet rigorous functional, performance goals. This is your opportunity to tackle complex technical challenges while contributing to products that shape the computing landscape.
Key Responsibilities
Develop and execute sophisticated verification plans to validate CPU logic against architectural and microarchitectural specifications
Create scalable, reusable verification environments using UVM-based testbenches and advanced functional coverage models
Perform in-depth functional coverage analysis, identify critical verification gaps, and implement strategic closure plans
Execute complex system-level simulations to validate functionality
Debug and perform root-cause analysis of issues in pre-silicon environments, implementing robust corrective measures
Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize verification workflows
Partner closely with CPU architects and RTL developers to verify complex architectural features
Maintain and enhance verification infrastructure, methodologies, and automation flows to maximize team productivity
Document comprehensive verification strategies and lead technical reviews with cross-functional stakeholders
Contribute to CPU architecture and microarchitecture feature definition to achieve optimal functional and performance targets
Qualifications:
Bachelor's or Master's degree in Electronics Engineering, Computer Engineering.
8+ years of experience in ASIC or FPGA design verification.
Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as System Verilog.
Strong hands-on experience in developing UVM-based testbenches and verification components.
Experience with RISC-V instruction set architecture.
Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB)
Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
Excellent analytical, problem-solving, and debugging skills.
Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.