{"id":34567,"url":"https://alion.io/job/altera-cpu-design-verification-engineer","title":"CPU Design Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":91,"open_postings":15,"ghost_share":0,"stale_share":0.333,"repost_share":0.067,"time_to_fill_p50_days":57,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-06-09T00:00:00Z","employer_posted_date":"2026-06-09","last_verified_at":"2026-10-16T17:09:23Z","board_verified":true,"closed_at":null,"days_open":130,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":130},"description":"Job Details:\nJob Description:\nAs a CPU Design Verification Engineer, you'll play a pivotal role in ensuring the functional correctness and performance of Altera's RISC-V processor family. Working alongside world-class CPU architects, RTL designers, and system design teams, you'll help validate designs that meet rigorous functional, performance goals. This is your opportunity to tackle complex technical challenges while contributing to products that shape the computing landscape.\nKey Responsibilities\nDevelop and execute sophisticated verification plans to validate CPU logic against architectural and microarchitectural specifications\n\nCreate scalable, reusable verification environments using UVM-based testbenches and advanced functional coverage models\n\nPerform in-depth functional coverage analysis, identify critical verification gaps, and implement strategic closure plans\n\nExecute complex system-level simulations to validate functionality\n\nDebug and perform root-cause analysis of issues in pre-silicon environments, implementing robust corrective measures\n\nDevelop automation scripts and tools using Python, Perl, C++, or similar languages to optimize verification workflows\n\nPartner closely with CPU architects and RTL developers to verify complex architectural features\n\nMaintain and enhance verification infrastructure, methodologies, and automation flows to maximize team productivity\n\nDocument comprehensive verification strategies and lead technical reviews with cross-functional stakeholders\n\nContribute to CPU architecture and microarchitecture feature definition to achieve optimal functional and performance targets\n\nQualifications:\nBachelor's or Master's degree in Electronics Engineering, Computer Engineering.\n\n8+ years of experience in ASIC or FPGA design verification.\n\nExpertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as System Verilog.\n\nStrong hands-on experience in developing UVM-based testbenches and verification components.\n\nExperience with RISC-V instruction set architecture.\n\nProficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).\n\nFamiliarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB)\n\nExperience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).\n\nStrong scripting skills in Python, Perl, or Tcl for automation and data analysis.\n\nExcellent analytical, problem-solving, and debugging skills.\n\nStrong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.\n\nJob Type:\nRegularShift:\nShift 1 (India)Primary Location:\nBengaluru, Karnataka, IndiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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