Design Verification Engineer
Job Details:
Job Description:
We're looking for a talented, self-motivated engineer to join our Design Verification team. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification.
This role is ideal for an early-career engineer who wants to build deep technical expertise in high-speed silicon verification. You'll work alongside experienced engineers on real silicon shipping to production, with plenty of opportunity to learn, grow, and take ownership as you ramp up.
What We Build
Our team develops and verifies high-speed SerDes IP - the physical layer technology that moves data across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters: the world's data moves through what we build.
What You'll Do
Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
Write testbenches, functional coverage models, and assertions
Run simulations, analyze failures, and debug both RTL and testbench issues
Collaborate with design, architecture, and analog teams on block-level and top-level verification
About Altera
Altera is the world's largest independent, pure-play FPGA company. Our programmable logic devices power data centers, telecommunications infrastructure, AI accelerators, and industrial systems. Recently spun out from Intel as an independent company, we combine decades of FPGA heritage with the focus and agility of a fresh start.
Qualifications:
BSc in Electrical Engineering, Computer Engineering, or equivalent
0-5 years of experience in digital design or verification (internships, academic projects, or industry)
Working knowledge of SystemVerilog and basic familiarity with UVM concepts
Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
Strong analytical and debug mindset - you enjoy getting to the bottom of a problem
Good communication skills in English (spoken and written)
Candidates should preferably be able to reside in Iași.