{"id":34524,"url":"https://alion.io/job/altera-design-verification-engineer","title":"Design Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":91,"open_postings":15,"ghost_share":0,"stale_share":0.333,"repost_share":0.067,"time_to_fill_p50_days":57,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":15500,"max_usd":37000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":633},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-07-29T00:00:00Z","employer_posted_date":"2026-07-29","last_verified_at":"2026-10-16T12:06:43Z","board_verified":true,"closed_at":null,"days_open":79,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":79},"description":"Job Details:\nJob Description:\nAltera is looking for a talented and drivenDesign Verification Engineer to Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.\nKey Responsibilities:\nCollaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.\n\nDevelop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).\n\nCreate and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.\n\nDevelop verification components, including drivers, monitors, scoreboards, and checkers.\n\nUtilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.\n\nExecute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.\n\nDefine and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.\n\nDevelop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.\n\nParticipate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.\n\nQualifications:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field .\n\n2+ years of experience in ASIC or FPGA design verification.\n\nExpertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.\n\nStrong hands-on experience in developing UVM-based testbenches and verification components.\n\nProficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).\n\nFamiliarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.\n\nExperience with simulation and debug tools.\n\nStrong scripting skills in Python, Perl, or Tcl for automation and data analysis.\n\nExcellent analytical, problem-solving, and debugging skills.\n\nStrong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.\n\nJob Type:\nRegularShift:\nShift 1 (India)Primary Location:\nRegus, MadhapurAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":2960,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-07-29T00:00:00Z"}],"visa":[],"liveness":{"score":24,"band":"cold","label":"Long shot","p_open":1,"p_active":0.55,"p_room":0.44,"age_days":79,"expected_fill_days":57,"reasons":["conf:28","velocity","win:tail","crowd:junior,brand"],"computed_at":"2026-10-16T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/altera-design-verification-engineer","json_url":"https://alion.io/job/altera-design-verification-engineer.json","meta":{"generated_at":"2026-10-16T12:18:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11425,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-design-verification-engineer"}]}