{"id":3312166,"url":"https://alion.io/job/altera-embedded-soft-ip-intern","title":"Embedded Soft IP Intern","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":12,"ghost_share":0,"stale_share":0.583,"repost_share":0.083,"time_to_fill_p50_days":56,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-26T00:00:00Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-10-31T07:08:23Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nAs an Embedded Soft IP intern in the Software, IP and Solutions (SIPS) group, you will work closely with the engineering team to design, verify and release RTL based IPs into Quartus as well as embedded reference designs. You will be exposed to industry practices and collaborate with a diverse team of hardware and software engineers working on Altera’s range of FPGA devices. From this experience, you will have a chance to build both wide and deep technical skills while contributing to designs used broadly across many industries.\nWe are looking for someone with the following qualities:\nPassion for learning, curious and has a growth mindset\nAble to work independently and effectively in a multi-site team environment\nFluent communication skills\nAble to problem solve and debug systematically\nGoal oriented and able to complete assignments on time and with quality\nYou will:\nContribute to process enhancements in both designing and validating existing and new IPs including scripting and implementing methodology improvements\nWrite functional tests, debug and potentially root cause regression failures, and propose solutions\nActively participate in team meetings, reviews and design discussions\nComprehend functional requirements and specifications of various IPs and designs\nExecute and run design flows, regressions and participate in design implementation.\nQualifications:\nPursuing a Bachelor’s or Master’s degree in Electrical, Computer or Electronics Engineering, Computer Science, or a comparable discipline\nStrong understanding of digital logic design and basic computer architecture\nFamiliar with scripting languages (Python, Perl, or TCL)\nFamiliar with System Verilog, Verilog, or VHDL\nExposure to FPGA design flows or tools (Quartus, Vivado, etc.)\nJob Type:\nStudent / Intern (Fixed Term)Shift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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