{"id":1139237,"url":"https://alion.io/job/altera-fpga-development-tools-engineer-5","title":"FPGA Development Tools Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"is_intermediary":false,"ats_vendor":"Workday","truth_index":{"grade":"A","score":95,"open_postings":21,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":88,"computed_at":"2026-09-23T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"structured","locations":["Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19500,"max_usd":43000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":438},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"GitLab CI","optional":false},{"name":"Jenkins","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Git","optional":true}],"status":"live","first_seen_at":"2026-09-23T09:52:13Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-23T06:29:35Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Details:\nJob Description:\nWe are seeking a senior engineer to join our Device Modeling & Enablement team. In this role, you will develop and automate tests used to validate FPGA device and simulation models used by Altera Quartus Prime. You’ll drive end-to-end validation flows, build and maintain regression infrastructure, analyze results, and collaborate with design teams to ensure high-quality releases across multiple device families. Ideal candidate has:\n- a strong foundation in digital design\n- hands on experience with FPGA/ASIC development flows\n- solid skill in automation and debug\n- a strong focus on quality and continuous improvement.\nKey Responsibilities\nTest Planning and Execution\nDevelop comprehensive test plans for device and simulation model validation across Quartus Prime components. \nExecute targeted and regression tests across multiple FPGA device families, configurations, and corner cases. \nEnsure verification coverage aligns with design intent and release quality goals.\nFlow and Infrastructure\nBuild and run end-to-end Quartus projects to exercise synthesis, fitting, and simulation signoff on representative designs. \nMaintain golden reference results; compare and triage deltas in QoR, performance, resource utilization, and warnings/errors. \nPackage and maintain reproducible test kits and reference designs. \nAutomation, Tooling, and Modeling\nCreate and maintain automation and modeling tools using C++, Tcl, Python, and bash for test generation, execution, log mining, and results reporting. \nDevelop and maintain C++ device model libraries representing FPGA architecture blocks such as DSP and memory used by synthesis and simulation flows. \nIntegrate tests and model validation into CI pipelines (e.g., Jenkins/GitLab CI), including pass/fail gates and artifact tracking. \nDevelop utilities to parameterize devices, architectural variants, corners, and random seeds for coverage expansion. \nDebug and Quality\nAnalyze failures across synthesis, fitter, and device models; isolate root causes across RTL, constraints, tool behavior, and C++ model implementations. \nCollaborate with modeling, device, and software teams to validate fixes and prevent regressions. \nTrack and improve key quality metrics (pass rate, coverage, defect density). \nDocumentation and Process\nAuthor and maintain test plans, runbooks, and user guides for test environments. \nContribute to checklists and acceptance criteria for device and model signoff. \nHelp improve validation process for better scalability and repeatability.\nQualifications:\nMinimum Qualifications\nBS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field\n4-5 year of relevant experience\nStrong foundation in digital design principles: combinational/sequential logic, clocking, resets, pipelining. \nExperience with FPGA or ASIC flows: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC). \nProficiency in at least one scripting language (Tcl or Python) and a working foundation in C++ for developing or debugging hardware or device models. \nFamiliarity with Linux development environments and build workflows. \nStrong problem-solving skills with the ability to interpret tool logs and timing reports. \nEffective written communication for documentation and clear defect reporting. \nPreferred Qualifications\nExperience developing or maintaining C++ libraries for hardware, architectural, or device modeling (e.g., DSP, memory, or timing models). \nExperience with Altera Quartus Prime (Lite/Standard/Pro), including TimeQuest and basic fitter concepts. \nHands-on experience with version control (Git) and CI systems (Jenkins/GitLab CI). \nFamiliarity with device concepts such as speed grades, PVT corners, IO standards, and clocking networks. \nBasic understanding of timing signoff concepts (clocks, generated clocks, I/O delays, false/multicycle paths). \nCoursework or projects involving FPGA boards, EDA tools, or regression test environments. \nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":4565,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Malaysia","iso":"MY","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Embedded Systems","Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-23T09:52:13Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":88,"reasons":["conf:9","win:early","comp:brand"],"computed_at":"2026-09-23T19:22:20Z"},"pay":null,"html_url":"https://alion.io/job/altera-fpga-development-tools-engineer-5","json_url":"https://alion.io/job/altera-fpga-development-tools-engineer-5.json","meta":{"generated_at":"2026-09-23T19:22:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}