{"id":2946811,"url":"https://alion.io/job/altera-fpga-development-tools-engineer-6","title":"FPGA Development Tools Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":60,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, 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Prime ecosystem.\nThis is a hands-on leadership role - you will:\nDefine technical direction \nLead complexproblem-solving \nActively contribute to design, modeling, and debugging \nYou will play a critical role in improving IP quality, simulation accuracy, and engineering productivity, while mentoring engineers and shaping best practices.\nKey Responsibilities\nTechnical Leadership (Hands-On)\nOwn technical direction for IP and simulation model \nLead design reviews, architecture discussions, and validation strategies \nDive deep into complex issues and personally drive resolution \nIP Development & Modeling\nDesign and implement FPGA IP(RTL/SystemVerilog/VHDL) \nDevelop high-fidelity simulation models: Behavioral \nCycle-accurate \n\nEnsure consistency between: Simulation models \nHardware implementation \n\nVerification & Validation Strategy\nDefine and enforce robust verificationmethodologies: SystemVerilog \nAssertion-based verification \n\nOversee and contribute to: Testbench architecture \nCoverage strategy \nRegression systems \n\nDebug & Root Cause Leadership\nLead debugging of complex issues across: Simulation \nFitter \nTiming analysis \n\nTranslate low-level issues into: Clear root cause \nActionable fixes \n\nQuartus Flow Integration\nEnsure seamless integration with: Compilation \nFitter \nTiming closure \n\nIdentify and drive improvements in: Tool usability \nDebuggability (e.g., Fitter insights) \n\nProductivity & Automation\nChampion engineering productivityimprovements: Automation frameworks (Python, Tcl) \nRegression infrastructure \nAI-assisted workflows (where applicable) \n\nMentorship & Team Development\nMentor engineers in: Debugging \nDesign quality \nVerification practices \n\nRaise overall team capability in: Root cause analysis \nSystem-level thinking\n\nQualifications:\nRequired Qualifications\nBachelor’s or Master’s in: Electrical Engineering / Computer Engineering \n8-12+ years of experience in: FPGA design, IP development, or verification \nStrong hands-on expertise in: RTL design(Verilog/SystemVerilog/VHDL)\nSimulation & verification \nDeep experience with: Altera Quartus Prime or equivalent FPGA toolchains \nProven ability to: Debug complex system-level issues andLead technical initiatives \nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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