{"id":4173669,"url":"https://alion.io/job/altera-fpga-ip-design-engineer-pey-intern","title":"FPGA IP Design Engineer - PEY Intern","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":15,"ghost_share":0,"stale_share":0.6,"repost_share":0.067,"time_to_fill_p50_days":54,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":90000,"max":100000,"currency":"CAD","period":"year","gross":null,"usd_annual":70220},"salary_estimate":null,"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-11-12T15:24:27Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T15:24:27Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Details:\nJob Description:\nThis internship is considered a PEY internship at our Toronto location with the expected start and end dates: May 3, 2027 - August 31, 2028.\nAbout the Role\nAltera is hiring a FPGA IP Design Engineer - Intern! As modern FPGAs become increasingly like a SoC, Altera's IP Engineering teams develop comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera's FPGA devices. We build IP cores to enable Memory Subsystems using External Memory Interfaces (like DDR5, LPDDR5) or High Bandwidth Memory (HBM) over a high speed NOC.\nThese IP cores provide configurable access to these high-speed, high-bandwidth memory devices. Most customers require some form of packet processing, storage or buffering, and thus, these IP cores become a critical component of most electronic systems.\nThe constantly rising speed and complexity of memory devices and interfaces presents a challenging design problem that requires system level knowledge of silicon, software, IP, and customer applications.\nAs an IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art Memory Interface or NoC-based IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.\nYour specific responsibilities will include, but are not limited to the following:\nArchitecture and Design based on the latest protocol specifications for memory, or NoC RTL development\nDevice support and CAD tool integration\nVerification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)\nHardware power-on and debug\nNew product release and rollout support\nCustomer technical support\nThe candidate should possess the following behavioral traits:\nStrong skills in communication, initiative, innovation, and teamwork\nHighly motivated to learn and adapt to fast-changing technologies and environments\nExcellent problem-solving skills and attention to detail\nDemonstrate fundamental values such as accountability, integrity, and a winning mindset\nCollaborative mindset, strong influencing skills, and a willingness to work across geographical locations.\nSalary\nOur compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge.\nEstimated Salary Range: $90,000 - $100,000 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.\nQualifications:\nMinimum Qualifications\nThe candidate must be pursuing a Bachelor's Degree in computer engineering, electrical engineering, engineering science, computer science, mathematics, or similar and 3+ months of experience or coursework in one, or more, of the following:\nSoftware programming and/or scripting (e.g. C/C++, Python), digital logic, RTL design (e.g. SystemVerilog, Verilog, VHDL), or similar \nPreferred Qualifications\nFPGA design experience, Experience with RTL simulation, timing closure, STA, Experience with Memory Interfaces.\nJob Type:\nStudent / Intern (Fixed Term)Shift:\nShift 1 (Canada)Primary Location:\nToronto, Ontario, CanadaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":4005,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","EDA Software"],"lifecycle":[{"event":"open","at":"2026-11-12T15:24:27Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":54,"reasons":["conf:2","win:early","comp:junior,brand"],"computed_at":"2026-11-12T17:41:04Z"},"pay":{"stated_usd_annual":70220,"is_top_pay":false},"html_url":"https://alion.io/job/altera-fpga-ip-design-engineer-pey-intern","json_url":"https://alion.io/job/altera-fpga-ip-design-engineer-pey-intern.json","meta":{"generated_at":"2026-11-12T17:41:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":37165,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-fpga-ip-design-engineer-pey-intern"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-fpga-ip-design-engineer-pey-intern"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-fpga-ip-design-engineer-pey-intern"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-fpga-ip-design-engineer-pey-intern\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-fpga-ip-design-engineer-pey-intern"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4173669}},{"tool":"search_jobs","arguments":{"company":"altera.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4173669},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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