{"id":934653,"url":"https://alion.io/job/altera-fpga-ip-software-development-engineer-4","title":"FPGA IP Software Development Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":17,"ghost_share":0,"stale_share":0.471,"repost_share":0.118,"time_to_fill_p50_days":53,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":50000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-14T00:00:00Z","employer_posted_date":"2026-09-14","last_verified_at":"2026-11-07T07:23:39Z","board_verified":true,"closed_at":null,"days_open":54,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":54},"description":"Job Details:\nJob Description:\nJob Summary\nAltera is seeking a Senior FPGA Soft IP Design Engineer to architect, develop, and productize FPGA Soft IP cores released through Quartus and Platform Designer.\nYou will own parameterizable RTL from micro-architecture through packaging, verification, and customer-ready delivery - producing reusable, high-performance IP that customers instantiate in production designs.\nThis role is for an experienced individual contributor who can take an IP from specification to Quartus catalog release, make sound PPA and interface trade-offs, and guide junior engineers. Hands-on experience with high-speed interface IP such as JESD204B/C or Ethernet is a strong plus.\nJob Responsibilities\nArchitect, design, and implement FPGA Soft IP cores in VHDL, Verilog, or System Verilog, targeting high performance, low resource usage, and timing closure across Altera device families.\nDevelop parameterizable, reusable IP with clean configuration spaces, documented interfaces, and stable upgrade behavior across Quartus releases.\nOwn the Soft IP lifecycle: RTL design, synthesis, functional simulation, lint, clock-domain crossing (CDC) analysis, static timing analysis (STA), and example-design bring-up.\nPackage IP for Quartus / Platform Designer (Qsys), including metadata, HDL generation, parameter validation, and integration with Native PHY, transceiver, and interconnect IP.\nDefine and implement register maps, CSR/AXI-Lite or Avalon-MM control interfaces, reset and clocking schemes, and user-facing data interfaces (AXI-Stream, Avalon-ST, or equivalent).\nDesign and maintain simulation testbenches, directed and constrained-random tests, assertions, and regression suites that prove protocol compliance and configuration coverage.\nCollaborate with verification, firmware, software, and hardware teams on memory maps, configuration sequences, example designs, and hardware validation on FPGA development kits.\nDebug IP issues across simulation, synthesis, place-and-route, and hardware; drive root-cause analysis and timely customer or release fixes.\nAuthor and review design specifications, user guides, release notes, and API/register documentation for internal teams and external customers.\nLead technical reviews, enforce coding and quality standards, and mentor junior Soft IP designers.\nSupport customer inquiries, FAEs, and design-in issues related to Soft IP behavior, integration, and performance.\nContribute to development-flow and quality improvements (lint/CDC/STA methodology, automation, IP upgrade robustness).\nQualifications:\nJob Qualifications\nMinimum qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related field.\nBachelor’s + 6 years, or Master’s + 4 years, of FPGA/ASIC RTL or Soft IP design.\nStrong proficiency in parameterizable RTL using Verilog, SystemVerilog, and/or VHDL.\nProven experience taking IP through synthesis, simulation, timing constraints (SDC), CDC, and STA.\nWorking knowledge of FPGA architecture, fabric resources, clocking, and the Quartus (or equivalent vendor) design flow.\nExperience packaging or integrating IP in Platform Designer / Qsys, Vivado IP Integrator, or a similar IP catalog flow.\nFamiliarity with on-chip interconnect and control protocols (AXI4 / AXI-Stream, Avalon-MM / Avalon-ST, CSR/register interfaces).\nExperience with scripting for IP generation, regression, and design automation (Python, Tcl, and/or Perl).\nProficiency with version control (Git) and structured code review.\nStrong debug, problem-solving, and written/verbal communication skills; able to work independently and lead technical discussions across sites.\n\nPreferred qualifications\nHands-on design or integration experience with high-speed interface Soft IP - JESD204B/C and/or Ethernet (MAC/PCS, TSE, or related)is a plus.\n8+ yearswith clear ownership of a production Soft IP (parameterization, packaging, release).\nExperience with other high-speed or memory interfaces (PCIe, CPRI, Interlaken, DDR) or with Soft IP that sits next to transceiver / Native PHY IP.\nKnowledge of protocol features such as deterministic latency, multi-lane alignment, FEC, or dynamic reconfiguration.\nExposure to SystemVerilog assertions, functional coverage, and coverage-driven verification (UVM experience is welcome but not required).\nFamiliarity with industry EDA tools (simulators, lint/CDC, synthesis) and hardware validation on FPGA development kits.\nPrior experience supporting Quartus IP catalog releases, example designs, or customer-facing IP documentation.\nDemonstrated technical leadership: mentoring, design reviews, and influencing architecture or methodology without formal people management.\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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