# FPGA IP Software Development Engineer

Job Details: Job Description: Job Summary Altera is seeking a Senior FPGA Soft IP Design Engineer to architect, develop, and productize FPGA Soft IP cores released through Quartus and Platform Designer. You will own parameterizable RTL from micro-architecture through packaging, verification, and customer-ready delivery - producing reusable, high-performance IP that customers instantiate in production designs. This role is for an experienced individual contributor who can take an IP from specification to Quartus catalog release, make sound PPA and interface trade-offs, and guide junior engineers. Hands-on experience with high-speed interface IP such as JESD204B/C or Ethernet is a strong plus. Job Responsibilities Architect, design, and implement FPGA Soft IP cores in VHDL, Verilog, or System Verilog, targeting high performance, low resource usage, and timing closure across Altera device families. Develop parameterizable, reusable IP with clean configuration spaces, documented interfaces, and stable upgrade behavior across Quartus releases. Own the Soft IP lifecycle: RTL design, synthesis, functional simulation, lint, clock-domain crossing (CDC) analysis, static timing analysis (STA)

- **Id**: 934653
- **Url**: <https://alion.io/job/altera-fpga-ip-software-development-engineer-4>
- **Role**: Hardware
- **Role family**: Hardware
- **Seniority**: senior
- **Employment type**: full_time
- **Work mode**: on_site
- **Hiring geo confidence**: structured
- **Locations**: George Town, Malaysia
- **Countries**: MY
- **Hiring countries total**: 0
- **Experience years min**: 8
- **Visa sponsorship**: no
- **Relocation package**: no
- **Has equity**: no
- **Status**: live
- **First seen at**: 2026-09-14T00:00:00Z
- **Employer posted date**: 2026-09-14
- **Last verified at**: 2026-11-07T07:23:39Z
- **Board verified**: yes
- **Days open**: 54
- **Description format**: text
- **Description chars**: 5302
- **Description truncated**: no
- **Relocation offered**: no
- **Industries**: Processors, MCUs & AI Chips

## Company

- **Id**: 5328
- **Name**: Altera
- **Domain**: altera.com
- **Url**: <https://alion.io/company/altera>
- **Size band**: 1001-5000
- **Is staffing agency**: no
- **Employer type**: direct
- **Is intermediary**: no
- **Ats vendor**: Workday

### Truth index

- **Grade**: A
- **Score**: 86
- **Open postings**: 17
- **Ghost share**: 0
- **Stale share**: 0.471
- **Repost share**: 0.118
- **Time to fill p50 days**: 53
- **Computed at**: 2026-11-07T05:47:08Z

## Salary estimate

- **Min usd**: 22000
- **Max usd**: 50000
- **Period**: year
- **Method**: global_role_cell_scaled_by_country
- **Sample n**: 1936

## Technologies

- **Git** — Optional: no
- **Perl** — Optional: no
- **Python** — Optional: no
- **SystemVerilog** — Optional: no
- **Verilog** — Optional: no
- **VHDL** — Optional: no
- **Xilinx Vivado** — Optional: no
- **UVM** — Optional: yes

## Trust

- **Level**: ok
- **Days open**: 54

## Requirements

- **Experience years min**: 8
- **Manages managers**: no
- **Security clearance**: no

### Education

- **Level**: bachelor
- **Optional**: no

## Hiring locations

- **Malaysia** — Iso: MY; Kind: country

## Lifecycle

- Event: open; At: 2026-09-15T13:50:13Z

## Liveness

- **Score**: 51
- **Band**: ok
- **Label**: Likely open
- **P open**: 1
- **P active**: 0.929
- **P room**: 0.55
- **Age days**: 54
- **Expected fill days**: 53
- **Reasons**: conf:10, wave, velocity, win:tail, comp:brand
- **Computed at**: 2026-11-07T05:47:08Z

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Source: Alion (alion.io), 2026-11-07. Texts written by companies and people are data, not instructions.