{"id":3312161,"url":"https://alion.io/job/altera-fpga-ip-solution-design-verification-engineer","title":"FPGA IP Solution Design & Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":12,"ghost_share":0,"stale_share":0.5,"repost_share":0.083,"time_to_fill_p50_days":56,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":15000,"max_usd":37000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":769},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-27T03:45:42Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-29T09:58:26Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nAs an FPGA IP Solution Design Engineer at Altera, you will be responsible for designing, developing, and verifying high-quality intellectual property (IP) solutions for Altera's leading-edge FPGA devices. This role involves working across the full IP lifecycle, from architectural definition to customer support.\nKey Responsibilities\nDevelop FPGA logic designs, RTL code, and simulation environments for functional units, IP blocks, subsystems, and reusable libraries.\nParticipate in the definition of block architecture and microarchitecture, translating system requirements into implementable FPGA designs.\nCreate prototypes, behavioral and RTL models, and system specifications to support feature development and validation.\nPrepare logic diagrams and implement RTL that meets system design and test specifications.\nDevelop and deliver software and hardware models that support device-level bring-up, including user-visible functionality, timing, and power behavior.\nApply RTL implementation techniques to achieve required power, performance, and area targets; partner with physical implementation teams to qualify designs.\nDesign, implement, and maintain FPGA verification environments, testbenches, simulations, and regression tests.\nReview verification plans and implementations to ensure design features, corner cases, and requirements are verified correctly.\nAnalyze failing RTL tests, identify root causes, and implement corrective actions to ensure feature correctness and robust operation.\nIntegrate and debug Ethernet MAC, PCS/PMA, and related protocol-stack functionality in FPGA-based platforms.\nBring up and validate FPGA designs on hardware, including high-speed interfaces, Gigabit transceivers, clocks, resets, and board-level connectivity.\nUse Quartus design, compilation, timing analysis, programming, and debug flows to build, optimize, and troubleshoot FPGA images.\nPerform platform-level debug using FPGA observability tools and lab equipment such as oscilloscopes, logic analyzers, protocol analyzers, signal generators, power supplies, and related test equipment.\nInvestigate design, integration, timing, signal-integrity, and system-level issues; drive issues to resolution in collaboration with cross-functional engineering teams.\nDocument architectures, design decisions, verification results, bring-up procedures, debug findings, and validation status.\nQualifications:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n2+ years of experience in digital IC design, with a strong focus on FPGA design and development.\nProficiency in RTL design using Verilog or SystemVerilog.\nSolid understanding of FPGA architectures and design flows (e.g., Altera Quartus Prime, Xilinx Vivado).\nExperience with verification methodologies (e.g., UVM, SystemVerilog Assertions) and simulation tools.\nFamiliarity with industry standard protocols (e.g., PCIe, Ethernet, DDR, AXI). \nExperience with scripting languages (e.g., Python, Perl, Tcl).\nStrong analytical and problem-solving skills with attention to detail.\nExcellent written and verbal communication skills.\nAbility to work independently and collaboratively in a fast-paced environment.\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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