FPGA Silicon Design Verification Engineer

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Job Description:

Job Summary

We are seeking a highly motivated FPGA Silicon Design Verification Engineer to join our hardware development team. The successful candidate will be responsible for pre-silicon verification of FPGA IP blocks, subsystems, and SoC-level designs. This role requires expertise in modern verification methodologies, strong debugging skills, and the ability to work closely with design, architecture, firmware, and validation teams to ensure first-pass silicon success.

The ideal candidate will have a solid background in SystemVerilog/UVM-based verification, functional coverage-driven verification, protocol verification, and FPGA or ASIC development flows.

Key Responsibilities

• Develop and execute comprehensive verification plans based on architecture and design specifications.
• Design, implement, and maintain reusable SystemVerilog/UVM verification environments, testbenches, sequences, and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define and track verification metrics, including functional coverage, code coverage, and assertion coverage.
• Develop SystemVerilog Assertions (SVA) to validate design behavior and identify corner-case issues.
• Perform debug and root-cause analysis of design failures using simulation, emulation, waveform analysis, and protocol analyzers.
• Collaborate closely with RTL designers, architects, and firmware teams to resolve functional and performance issues.
• Participate in design reviews, verification reviews, and project milestone assessments.
• Drive verification closure and ensure quality signoff before tape-out or FPGA release.
• Support post-silicon bring-up and validation activities as needed.
• Contribute to verification methodology improvements, automation, and regression infrastructure.

Qualifications:

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of experience in digital design verification for FPGA or ASIC products.
• Strong expertise in:
  • SystemVerilog
  • UVM (Universal Verification Methodology)
  • Assertion-Based Verification (ABV)
  • Constrained-random verification methodologies
• Solid understanding of digital design fundamentals, including:
  • Clock domain crossings (CDC)
  • Reset synchronization
  • Pipelines
  • State machines
  • Memory architectures
• Experience with industry-standard simulators such as:
  • Synopsys VCS
  • Cadence Xcelium
  • Siemens QuestaSim
• Experience developing verification components, scoreboards, monitors, agents, and coverage models.
• Strong debugging skills using waveform viewers and simulation tools.
• Proficiency with scripting languages such as Python, Perl, Tcl, or Shell scripting.
• Experience with version control systems such as Git.

Preferred Qualifications

• Experience verifying FPGA-based networking, storage, compute acceleration, or high-speed interface IP.
• Knowledge of industry-standard protocols such as:
  • PCI Express (PCIe)
  • Ethernet
  • AXI/AHB/APB
  • DDR Memory Interfaces
  • CXL
  • Serial communication protocols
• Experience with coverage-driven verification and verification closure methodologies.
• Familiarity with formal verification tools and methodologies.
• Experience with FPGA platforms from Intel (Altera) or AMD/Xilinx.
• Experience with emulation, FPGA prototyping, or hardware acceleration environments.
• Knowledge of DFT, scan architecture, and silicon bring-up processes.
• Familiarity with CI/CD flows and automated regression systems.

Technical Skills

• SystemVerilog
• UVM
• SVA
• Functional Coverage
• Regression Automation
• Python/Perl/Tcl
• Git or equivalent version control systems

Desired Traits

• Strong analytical and problem-solving skills and attention to detail.
• Excellent communication and collaboration abilities.
• Ability to work effectively in a fast-paced development environment.
• Self-driven with a focus on quality and execution.
• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

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