{"id":93807,"url":"https://alion.io/job/altera-fpga-silicon-design-verification-engineer-3","title":"FPGA Silicon Design Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":14,"ghost_share":0,"stale_share":0.571,"repost_share":0.071,"time_to_fill_p50_days":56,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"CI/CD","optional":true},{"name":"Git","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"closed","first_seen_at":"2026-08-11T00:00:00Z","employer_posted_date":"2026-08-11","last_verified_at":"2026-11-01T08:23:03Z","board_verified":false,"closed_at":"2026-11-01T08:23:03Z","days_open":82,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":82},"description":"Job Details:\nJob Description:\nPosition Summary\nWe are seeking a highly motivated Design Verification (DV) Engineer to verify Design-for-Test (DFT) and test-related logic for complex SoC and IP designs on our flagship FPGAs. The successful candidate will be responsible for developing and executing comprehensive pre-silicon verification plans, creating UVM-based testbenches, and ensuring high-quality silicon through rigorous verification methodologies.\nKey Responsibilities\nDevelop and execute verification plans for DFT and test logic features, including scan, MBIST, LBIST, JTAG, boundary scan, and related infrastructures.\nCreate and maintain SystemVerilog/UVM-based verification environments.\nDevelop reusable verification components, sequences, scoreboards, assertions, and coverage models.\nVerify DFT architectures and test modes at IP, subsystem, and SoC levels.\nPerform functional, regression, and coverage-driven verification.\nAnalyze simulation failures, debug RTL and testbench issues, and drive root cause resolution.\nCollaborate closely with DFT architects, design engineers, validation teams, and physical design teams.\nReview specifications and provide feedback on testability and verification requirements.\nTrack verification metrics, functional coverage, code coverage, and regression results.\nQualifications:\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n5+ years of ASIC/SoC design verification experience.\nStrong expertise in SystemVerilog and UVM methodology.\nExperience verifying DFT features such as: Scan insertion and scan compression\nMBIST\nLBIST\nJTAG / IEEE 1149.x\nBoundary scan\nTest access mechanisms\n\nStrong debugging skills in simulation environments.\nExperience with industry-standard simulators such as VCS, Xcelium, or Questa.\nKnowledge of assertions (SVA), constrained-random verification, and coverage-driven methodologies.\nPreferred Qualifications\nExperience with SoC-level verification.\nFamiliarity with ATPG concepts and test pattern generation.\nKnowledge of low-power verification methodologies.\nExperience with scripting languages such as Python, Perl, or Tcl.\nUnderstanding of CI/CD and automated regression environments.\nExperience mentoring junior verification engineers.\nTechnical Skills\nSystemVerilog\nUVM\nSVA\nDFT Architectures\nScan/MBIST/LBIST/JTAG\nFunctional Coverage\nRegression Automation\nPython/Perl/Tcl\nGit or equivalent version control systems\nDesired Traits\nStrong analytical and problem-solving skills and attention to detail.\nExcellent communication and collaboration abilities.\nAbility to work effectively in a fast-paced development environment.\nSelf-driven with a focus on quality and execution.\nDemonstrate fundamental values such as accountability, integrity, and a winning mindset\nJob Type:\nRegular Shift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\n Posting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical 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