{"id":2946812,"url":"https://alion.io/job/altera-fpga-silicon-design-verification-engineer-8","title":"FPGA Silicon Design Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":60,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Java","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verification & Validation","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-09-17T00:00:00Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-10-22T10:47:32Z","board_verified":true,"closed_at":null,"days_open":35,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":35},"description":"Job Details:\nJob Description:\nFrom the IoT to the data center, Altera offers a broad portfolio of programmable logic solutions that allow customers to solve a wide variety of system level challenges.\nBe part of the talented PCIe IP design verification team\n\nWe are looking for experienced IP design verification engineer\n\nResponsibility includes\nCreate comprehensive verification plan based on FPGA IP architecture specifications and carry out all the IP verification tasks. Developing IP, subsystem or system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Review verification and validation results against the coverage goals. Writing, analysing and achieving coverage metrics with failures debugging as well as bug filling and closure. Interfacing with 3rd party vendors for latest industry tool and methodology or VIP exposure and evaluation Understanding and enhancement of Design Verification processes in the FPGA development flow Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time to market. Provide practical, innovative solutions to complex problems.\nThis role requires excellent communication and leadership skills and a proven ability to work with challenging schedules. Join our team of innovators to push the boundaries of what’s possible and move into the future.\nQualifications:\nMSEE/BSEE or equivalent with 5 years of experience in IP / SoC design verification.\n\nStrong in System Verilog, UVM, Verilog\n\nStrong in coverage-based verification methodology with assertions\n\nKnowledge on PCIe is a must\n\nFamiliar with Perl, Python, Java is a plus\n\nFamiliarity with Intel Quartus or Xilinx Vivado is a plus.\n\nStrong skills in communication, initiative, promote innovation and teamwork\n\nHighly motivated to learn and adapt to fast changing technologies and environments\n\nDemonstrates fundamental values such as accountability, integrity and a winning mindset\n\nJob Type:\nRegularShift:\nShift 1 (India)Primary Location:\nBengaluru, Karnataka, IndiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":2553,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Cybersecurity","Hardware","Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-20T18:53:46Z"}],"visa":[],"liveness":{"score":75,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.829,"p_room":0.9,"age_days":35,"expected_fill_days":60,"reasons":["conf:3","velocity","win:mid","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/altera-fpga-silicon-design-verification-engineer-8","json_url":"https://alion.io/job/altera-fpga-silicon-design-verification-engineer-8.json","meta":{"generated_at":"2026-10-22T13:21:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12528,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-fpga-silicon-design-verification-engineer-8"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-fpga-silicon-design-verification-engineer-8"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-fpga-silicon-design-verification-engineer-8"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-fpga-silicon-design-verification-engineer-8\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-fpga-silicon-design-verification-engineer-8"}]}