HLD Validation Technical Lead

Job Details:

Job Description:

• Researches, designs, develops, and optimizes software tools that enable the use of Field Programmable Gate Arrays (FPGA).
• Develops and optimizes compilers, flows, assemblers, models, tools, runtimes, and/or firmwares that are closely coupled to FPGA silicon, IP, and boards, while leveraging strong knowledge of FPGA hardware, logic design, board design, semiconductor devices, and chip layout.
• Designs, develops, and optimizes software abstractions and frameworks for acceleration with the FPGA for domains such as deep learning, DSP algorithms, or data analytics. Responds to customer/client requests or events as they occur.

Qualifications:

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Software Engineering, or a related field.
• 8+ years of experience in FPGA development, software-tool verification, or validation, including substantial hands-on work with FPGA design flows.
• 3+ years of technical leadership, project leadership, or equivalent experience guiding engineers and coordinating complex validation work.
• Strong understanding of FPGA architectures and tool flows from design entry through compilation, simulation, implementation, timing analysis, and hardware execution.
• Experience developing validation strategies, test plans, regression suites, defect reports, and release-quality assessments for complex software tools.
• Proficiency with scripting and automation, such as Python, Perl, Tcl, or shell, and experience with CI/CD or automated regression infrastructure.
• Demonstrated ability to debug cross-layer software and FPGA issues, analyze results, make risk-based recommendations, and communicate findings to technical and nontechnical stakeholders.
• Strong collaboration, mentoring, and written and verbal communication skills in a cross-functional environment.

Preferred qualifications

• Direct experience using or validating at least one HLD tool category: high-level synthesis, DSP-oriented design, AI-oriented FPGA tools, compiler flows, or design-generation tools. Experience with FPGA AI Suite, HLS Compiler, or DSP Builder is especially valuable.
• Hands-on experience with Altera/Intel Quartus Prime or comparable FPGA development tools from other vendors.
• Familiarity with Verilog or VHDL; simulation, waveform, synthesis, place-and-route, and timing-analysis tools.
• Experience with FPGA development kits, board-level testing, SoC integration, PCIe or embedded flows, or hardware/software bring-up.
• Experience with Linux and Windows test environments, containers, virtual machines, and shared lab infrastructure.
• Experience with performance characterization, AI model benchmarking, test-result analysis, and automated reporting.
• Experience with UI automation using Playwright, Selenium, or comparable tools where applicable to the supported product flows.

Success measures

• Validation coverage and release criteria remain aligned with HLD product requirements, customer workflows, and release commitments.
• Critical defects and coverage gaps are identified early, communicated with clear impact, and resolved or given an explicit release disposition.
• Regressions, environments, and reports are reliable, maintainable, and usable by other engineers without dependence on a single individual.
• Automation improves repeatability, useful coverage, triage speed, and reporting consistency while reducing avoidable manual effort.
• Stakeholders receive timely, evidence-based assessments of validation status and release risk.
• Validation engineers receive effective technical guidance and grow in ownership of their work.

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