{"id":3241861,"url":"https://alion.io/job/altera-ip-design-pey-intern","title":"IP Design PEY Intern","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":60,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"C++","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true}],"status":"live","first_seen_at":"2026-10-23T00:00:00Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-25T21:23:12Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nAbout Altera\nAt Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.\nAbout the Role\nJoin Altera IP solutions team and work on cutting edge FPGA RTL and IP design! Altera's IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera’s FPGA devices. These solutions are provided as highly configurable intellectual property (IP) cores that are fully integrated with Altera's software CAD tool, Quartus Prime. The External Memory Interfaces (EMIF) and IO team is responsible for developing IPs for communication with state-of-the-art DDR and LPDDR devices, MIPI cameras and sensors, and other high-speed I/O applications. The ever-growing demand for faster I/O interfaces - especially in the data center and machine learning sectors - presents a challenging design problem that requires system-level knowledge of silicon, software, IP, and customer applications.\nYou will work with a team of engineers to develop and verify state-of-the-art IP cores for interfacing with external memories and other I/O devices. You will be working on advanced FPGA architectures, design definition, implementation, and verification. Additionally, you will also be developing design examples and simulation models, accompanied by a rich set of technical documentation. In this role, you will work closely with multiple teams, including silicon design and validation, post-silicon validation, application engineering, and customer experience teams, to ensure seamless development, integration, and optimization of high-speed interface IP solutions.\nYour specific responsibilities will include, but are not limited to the following:\nArchitecture and Design based on the latest protocol specifications for DDR, LPDDR, and MIPI devices\nRTL development\nDevice support and CAD tool integration\nVerification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)\nHardware power-on and debug\nNew product release and rollout support\nCustomer technical support \nThe candidate should possess the following behavioral traits:\nStrong skills in communication, initiative, innovation, and teamwork\nHighly motivated to learn and adapt to fast-changing technologies and environments\nExcellent problem-solving skills and attention to detail\nDemonstrate fundamental values such as accountability, integrity, and a winning mindset\nCollaborative mindset, strong influencing skills, and a willingness to work across geographical locations\nSalary\nOur compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.\nEstimated Salary Range: $90,000 - $100,000 CAD\nWe use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.\nQualifications:\nYou must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications:\nCurrently pursuing a BS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or related field\n3+ months of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification\n3+ months of experience in scripting languages and/or software programming (e.g. Python/TCL/Perl and/or C/C++) \nPreferred Qualifications:\nFPGA design experience\nExperience with RTL simulation, timing closure and static timing analysis\nExperience with DDR, LPDDR, or MIPI hardware interfaces\nJob Type:\nStudent / Intern (Fixed Term)Shift:\nShift 1 (Canada)Primary Location:\nToronto, Ontario, CanadaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":5359,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Cybersecurity","Hardware","Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-25T16:42:19Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":3,"expected_fill_days":60,"reasons":["conf:6","win:early","comp:junior,brand"],"computed_at":"2026-10-26T04:22:42Z"},"pay":null,"html_url":"https://alion.io/job/altera-ip-design-pey-intern","json_url":"https://alion.io/job/altera-ip-design-pey-intern.json","meta":{"generated_at":"2026-10-26T04:22:42Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5996,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-ip-design-pey-intern"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-ip-design-pey-intern"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-ip-design-pey-intern"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-ip-design-pey-intern\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-ip-design-pey-intern"}]}