{"id":3312162,"url":"https://alion.io/job/altera-lead-design-verification-engineer-3","title":"Lead Design Verification Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":12,"ghost_share":0,"stale_share":0.5,"repost_share":0.083,"time_to_fill_p50_days":56,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":67000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-27T03:45:42Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-29T09:58:26Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nPerforms functional logic verification of an FPGA to ensure design will meet specification requirements.\n\nDevelops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.\n\nExecutes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.\n\nReplicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.\n\nCollaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.\n\nMay also collaborate with systems and software engineers to support integration testing of the FPGA.\n\nDocuments test plans and drives technical reviews of plans and proofs with design and architecture teams.\n\nMaintains and improves existing functional verification infrastructure and methodology.\n\nDocuments, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.\n\nQualifications:\nMinimal Qualification:\nCandidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience.\nRelated technical experience should be in/with: Pre Silicon Validation/Verification.\nOVM/UVM, System Verilog, constrained random verification methodologies.\nPreferred Qualification:\nDesign Verification with developing, maintaining, and executing complex IPs and/or SOCs.\nThe complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).\nDeveloping validation test suites and driving continuous improvement into existing validation test suites and methodologies.\nExperience in PCIe or UCIe PHY Verification.\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender 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