{"id":93840,"url":"https://alion.io/job/altera-principal-noc-ip-micro-architect-2","title":"Principal NoC IP Micro-Architect","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":14,"ghost_share":0,"stale_share":0.5,"repost_share":0.071,"time_to_fill_p50_days":53,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Networking","role_family":"Networking","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":55000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":205},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false}],"status":"live","first_seen_at":"2026-06-16T00:00:00Z","employer_posted_date":"2026-06-16","last_verified_at":"2026-11-10T14:59:04Z","board_verified":true,"closed_at":null,"days_open":147,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":147},"description":"Job Details:\nJob Description:\nDevelops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.\n\nParticipates in the definition of architecture and microarchitecture features of the block being designed.\n\nCreates prototypes, simulates models, and specifies systems requirements.\n\nPrepares and designs logic diagrams and codes for implementing system design and test specifications.\n\nDelivers software models for device level bring up, including user visible functionality, timing, and power.\n\nApplies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.\n\nStrong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency.\n\nReviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.\n\nAs a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.\n\nQualifications:\nBachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.\n\nExperience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis\n\nExperience in programming with C/C++/Perl/Python/TCL/Unix Shell script\n\nExperience in FPGA design and programming is a plus.\n\nExperience in RTL validation is a plus.\n\nExperience in development of Network on Chip IPs.\n\nExperience with the usage of AI with development process for high efficiency development would be a great plus.\n\nAbility to work with different teams, good communication and problem-solving skills.\n\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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