{"id":34540,"url":"https://alion.io/job/altera-principal-noc-ip-micro-architect","title":"Principal NoC IP Micro-Architect","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":14,"ghost_share":0,"stale_share":0.571,"repost_share":0.071,"time_to_fill_p50_days":56,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Networking","role_family":"Networking","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":209500,"max":299200,"currency":"USD","period":"year","gross":null,"usd_annual":299200},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false}],"status":"live","first_seen_at":"2026-07-15T00:00:00Z","employer_posted_date":"2026-07-15","last_verified_at":"2026-11-03T07:28:39Z","board_verified":true,"closed_at":null,"days_open":111,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":111},"description":"Job Details:\nJob Description:\nAbout Altera\nAt Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.\nAbout the Role\nAs a Principal NoC IP Micro-Architect, you will be responsible for the end-to-end architecture, microarchitecture, RTL design, and technical leadership of scalable NoC IP solutions integrated into Altera's next-generation FPGA platforms. You will work closely with architecture, design, verification, software, physical design, and product teams to deliver high-performance interconnect solutions optimized for power, performance, area (PPA), scalability, and reliability.\nThis is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system-level optimization.\nKey Responsibilities\nDevelops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.\n\nParticipates in the definition of architecture and microarchitecture features of the block being designed.\n\nCreates prototypes, simulates models, and specifies systems requirements.\n\nPrepares and designs logic diagrams and codes for implementing system design and test specifications.\n\nDelivers software models for device level bring up, including user visible functionality, timing, and power.\n\nApplies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.\n\nStrong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency.\n\nReviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.\n\nAs a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.\n\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$209,500 - $299,200 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications:\nBachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.\n\n10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis\n\n10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script\n\n10+ years of experience in FPGA design and programming is a plus.\n\n10+ years of experience in RTL validation is a plus.\n\n10+ years of experience in development of Network on Chip IPs.\n\n5+ years of experience with the usage of AI with development process for high efficiency development would be a great plus.\n\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":4617,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-07-15T00:00:00Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 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