{"id":1924390,"url":"https://alion.io/job/altera-product-architectural-model-development-leader","title":"Product Architectural Model Development Leader","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":14,"ghost_share":0,"stale_share":0.214,"repost_share":0.071,"time_to_fill_p50_days":71,"computed_at":"2026-10-08T05:49:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":341075,"currency":"USD","period":"year","gross":null,"usd_annual":341075},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-05T19:18:15Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-09T00:12:21Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nPosition Summary\nAltera is seeking a Product Architecture Model Development Leader to drive the creation, quality, and evolution of behavioral and architectural models that represent next-generation FPGA silicon before and during RTL development.\nThis role sits at the intersection of architecture, verification, software enablement, and customer enablement - the behavioral models you and your team build become the single source of truth used by architects for pathfinding and performance analysis, by verification teams for golden-reference checking, by RTL design teams as an internal product reference for intended behavior, and by software/compiler teams for early enablement, long before silicon or even RTL exists. These models will also enable customers earlier in the product lifecycle through pre-silicon functional simulation, early RTL and data-flow development, and software and driver development ahead of device availability.\nYou will lead a team of model developers and set the technical direction for how Altera represents FPGA fabric, hard IP, and system-level behavior in executable, simulatable form.\nKey Responsibilities\nTechnical Leadership\nLead a team of behavioral modeling engineers responsible for developing cycle-approximate and functional models of FPGA architecture (fabric, DSP blocks, memory hierarchies, hard IP, transceivers, NoC, etc.)\nDefine modeling methodology, coding standards, and architecture for behavioral models (C++, SystemC, Python) used across the pre-silicon design flow\nOwn the roadmap for model development in lockstep with architecture definition milestones - from early concept and pathfinding through RTL freeze\nDrive model accuracy, performance, and maintainability trade-offs, ensuring models scale across increasingly complex FPGA generations\nCross-Functional Model Ownership\nPartner with silicon architects to translate architectural specifications and microarchitecture decisions into executable behavioral models\nEstablish the architectural model as a trusted internal product reference for intended system behavior, functional flows, interfaces, and architectural rules across architecture, design, verification, firmware, and software teams\nCollaborate with verification teams to ensure behavioral models serve as golden references / scoreboards for RTL verification (UVM environments, formal checking, co-simulation)\nWork with performance modeling and pathfinding teams to support design-space exploration, power/performance/area (PPA) trade-off studies, and early customer workload analysis\nDrive early customer enablement by delivering models that support pre-silicon prototyping, functional simulation, RTL and data-flow development, and evaluation of product capabilities before silicon availability\nSupport software, firmware, compiler, driver, and tools teams that depend on behavioral models for early development, platform bring-up, and functional simulation ahead of silicon availability\nWork with Quartus and customer-facing engineering teams to evolve models into early product representations that allow customers and FAEs to begin development sooner and reduce time to first successful design on new devices\nInterface with RTL design teams to resolve model-vs-RTL discrepancies and maintain model/RTL equivalence throughout the design cycle\nProcess and Infrastructure\nEstablish and maintain simulation infrastructure, regression frameworks, and CI pipelines for model validation\nDrive model versioning, documentation, and configuration management practices so models remain a trusted reference across multiple concurrent projects/generations\nChampion automation to reduce hand-off latency between architecture spec, model, RTL, and verification\nIdentify opportunities to leverage or build tooling (e.g., model generators, spec-to-model flows) that improve modeling velocity and reduce spec ambiguity\nPeople Leadership\nHire, mentor, and grow a team of behavioral/architecture modeling engineers\nSet individual and team goals aligned with architecture program milestones\nFoster close working relationships between the modeling team and adjacent architecture, verification, and design organizations\nCore Competencies\nStrong architectural and systems-level thinking - able to reason about hardware behavior at multiple levels of abstraction\nRigor and precision in translating ambiguous specs into unambiguous, testable model behavior\nLeadership style that balances deep technical involvement with team development and delegation\nAbility to manage competing priorities across multiple concurrent silicon programs\nStrong collaborator across architecture, verification, RTL design, and software organizations\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231,500 - $341,075 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field (Master's or PhD preferred)\n15+ years of experience in silicon architecture, design, or verification, with 5+ years in a technical leadership role\nStrong hands-on experience developing behavioral, functional, or performance models in C++, SystemC, and/or System Verilog\nDeep understanding of FPGA or ASIC architecture fundamentals (fabric architecture, memory subsystems, interconnect, hard IP blocks)\nExperience bridging architecture specifications into simulatable models used for verification and/or performance analysis\nExperience using pre-silicon models to enable software, firmware, drivers, or customer development ahead of RTL or silicon availability\nFamiliarity with RTL design and verification flows (SystemVerilog/UVM) sufficient to reason about model-RTL equivalence\nTrack record of leading technical teams delivering complex infrastructure/models on multi-quarter silicon program timelines\nStrong communication skills - able to represent modeling team priorities to architecture leadership and coordinate across verification, design, and software orgs\nPreferred Qualifications:\nPrior experience specifically with FPGA architecture ( embedded memory, transceivers, NoC/interconnect)\nExperience with performance/pathfinding modeling for PPA trade-off studies\nExperience building or maintaining spec-to-model or model-to-RTL automation/codegen flows\nFamiliarity with formal methods or golden-model-based verification methodologies\nExperience supporting early software/compiler enablement using pre-silicon models\nExperience delivering customer-consumable pre-silicon models or integrating architectural models into FPGA/ASIC development tools for early customer prototyping\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":7611,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-05T19:18:15Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 71","filings_12m":71,"filings_prev_12m":39,"green_card_filings_12m":0,"median_offered_wage_usd":157500,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":47}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":71,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-10-08T05:49:30Z"},"pay":{"stated_usd_annual":341075,"is_top_pay":true},"html_url":"https://alion.io/job/altera-product-architectural-model-development-leader","json_url":"https://alion.io/job/altera-product-architectural-model-development-leader.json","meta":{"generated_at":"2026-10-09T01:04:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1737,"day_limit":5000,"remaining_today":3263,"minute_limit":60,"resets_at":"2026-10-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-product-architectural-model-development-leader"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-product-architectural-model-development-leader"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-product-architectural-model-development-leader"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-product-architectural-model-development-leader\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-product-architectural-model-development-leader"}]}