{"id":786961,"url":"https://alion.io/job/altera-senior-director-silicon-hardware-engineering-boards-packaging-reliability","title":"Senior Director, Silicon Hardware Engineering - Boards, Packaging, & Reliability","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":57,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"head","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":335000,"currency":"USD","period":"year","gross":null,"usd_annual":335000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys SIwave","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"HyperLynx","optional":false}],"status":"live","first_seen_at":"2026-09-10T00:00:00Z","employer_posted_date":"2026-09-10","last_verified_at":"2026-10-27T03:45:42Z","board_verified":true,"closed_at":null,"days_open":47,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":47},"description":"Job Details:\nJob Description:\nAbout Altera\nAt Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.\nAbout the Role\nWe are seeking a seasoned and technically deep engineering leader to serve as Senior Director of Silicon Hardware Engineering - Boards, Packaging & Reliability, leading a global, distributed organization spanning chip package development, board hardware development, and silicon power and reliability engineering. Reporting directly to the VP of Engineering, this leader will be accountable for defining and executing the technical strategy, development methodologies, and organizational capabilities required to deliver high-performance, reliable silicon hardware solutions at scale. The ideal candidate combines hands-on technical expertise and sound engineering judgment in advanced semiconductor technologies with a proven track record of operational excellence, cross-functional collaboration, and building and leading high-performing engineering organizations across U.S. and Asia sites.\nKey Responsibilities\nTeam & Organizational Leadership\nLead,develop, and scalethree core engineering functions: chip package development, board hardware development, and silicon power and reliability engineering.\n\nBuild, mentor, and develop high-performing engineering teams distributed across the U.S. and Asia, fostering a collaborative,accountable, andresults-driven culture.\n\nPartner closely with VP/SVP leadership to define multi-yeartechnicalroadmaps, headcount plans, and organizational strategy.\n\nEstablish clear goals, KPIs,engineering standards,and performance expectations across all teams.\n\nDrive technical and organizational alignment across the three functions to improve execution, quality, and predictability across product programs.\n\nTechnical Excellence\nDefine and drive technical direction foradvanced package technologies including 2.5D/3D IC, flip-chip, and high-density interconnect.\n\nOversee board-level hardware development from concept through bring-up, ensuring design-for-manufacturability and design-for-test.\n\nChampion rigorous signal integrity (SI) and power integrity (PI) methodologies, ensuringconsistent engineering standards andadoption of best-in-class EDA tooling across teams.\n\nLead silicon power and reliability programs including power budgeting, electromigration, ESD, and reliability qualification.\n\nApply deep knowledge of silicon design development methodologies to improve tapeout quality, schedule, and first-pass silicon success rates.\n\nDrive disciplined technical reviews and engineering decision-making across package, board, SI/PI, power, and reliability activities to identify and mitigate product risks early.\n\nProgram Execution, Operations & Vendor Management\nOwn end-to-endengineeringprogram execution across multiple concurrent programs, driving on-time and on-budget delivery.\n\nDevelop and execute cost-reduction strategies across packaging, board materials, and test processes without compromising qualityor product requirements.\n\nManage complex, multi-vendor relationships with OSATs, PCB fabricators, substrate suppliers, and EDA vendors.\n\nImplement robust supplier qualification, scorecard, and escalation processes to ensuresupplier performance andsupply chain resilience.\n\nDrive continuous improvement in cycle time and cost through data-driven operational reviews.\n\nEstablish clear execution metrics, risk-management mechanisms, and escalation paths to improve predictability across development programs.\n\nCross-Functional & Executive Leadership\nServe as the primary engineering interface for internal customers including silicon architecture, SoC design, system integration, and product management teams.\n\nPartner across engineering functions to ensure package, board, power, reliability, and silicon development requirements are aligned throughout the product-development lifecycle.\n\nRepresent hardware engineering in executive reviews, customer engagements, and technology partnership discussions.\n\nCommunicate complex technical tradeoffsand associated cost, schedule, quality, and product implicationsclearly to non-technical stakeholders and senior leadership.\n\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231,500 - $335,000 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or closely related field required; Master's Degree preferred.\n\n15+ years of progressive experience in semiconductor hardware engineering, with at least 5 years in a senior leadership or director-level role.\n\nDemonstrated experience managing global, cross-functional engineering teams across U.S. and Asian sites.\n\nDeep technical expertise in chip package development, including advanced packaging, substrate design, and OSAT management.\n\nProven experience in chip board hardware development, including schematic design, PCB layout, and bring-up.\n\nStrong hands-on background in signal integrity and power integrity analysisand methodologies, including experience with industry-standard tools such as Ansys SIwave, Cadence Sigrity, HyperLynx, or equivalent.\n\nSolid understanding of silicon design development methodologies, including synthesis, place and route (P&R), timing closure, and DFT.\n\nTrack record of delivering measurable cost-reduction programs across package and board hardwarewhile maintaining product quality and technical requirements.\n\nExperience managing and qualifying multiple external vendors and OSATs simultaneously.\n\nDemonstrated ability to drive complex engineering programs and technical decisions across organizational boundaries.\n\nExcellent communication,influencing,and executive presentation skills.\n\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, 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