{"id":2946806,"url":"https://alion.io/job/altera-senior-fpga-ip-design-engineer","title":"Senior FPGA IP Design Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":57,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Synopsys VCS","optional":false}],"status":"live","first_seen_at":"2026-10-20T18:53:46Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-25T21:23:12Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nWe are seeking a Senior FPGA Soft IP Development Engineer to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores-including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures.\nResponsibilities\nOwn micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces\nCollaborate closely with the verification team to shape test plans and improve verification coverage\nWork with the physical design team to understand and resolve timing, power, and congestion challenges\nWork with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary\nProvide technical support to the FAE team on pre-sales customer engagements\nProvide technical support to the AE team on post-sales customer deliveries\nApply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow\nDevelop RTL micro-architecture from scratch\nProvide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor\nRequired Qualifications & Technical Skills\nEducation & Experience: bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5+ years of dedicated RTL/FPGA design experience.\nProtocol Expertise: Deep, hands-on knowledge of the AMBA AXI4 protocol suite and high-speed memory interfaces.\n Toolchains: Proficiency with FPGA implementation tools and EDA simulation software (Siemens Questa/Modelsim, Synopsys VCS).\nScripting: Strong scripting skills in Python, Tcl, or Perl for build automation and test automation.\nQualifications:\nJob Type:\nRegularShift:\nShift 1 (India)Primary Location:\nBengaluru, Karnataka, IndiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national 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