{"id":557248,"url":"https://alion.io/job/altera-senior-fpga-rtl-and-firmware-development-engineer","title":"Senior FPGA RTL and Firmware Development Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":16,"ghost_share":0,"stale_share":0.563,"repost_share":0,"time_to_fill_p50_days":53,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":51000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"AI Agents","optional":true},{"name":"CI/CD","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-09-08T23:13:22Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-11-14T16:48:09Z","board_verified":true,"closed_at":null,"days_open":67,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":67},"description":"Job Details:\nJob Description:\nPosition Overview\nAltera is seeking an experienced FPGA RTL and Firmware Development Engineer to join the Platform Hardware Board Engineering team. This role is intended for a hands-on technical contributor with 10+ years of FPGA RTL design experience and practical firmware development capability. The engineer will own or lead FPGA-based platform solutions spanning RTL architecture, implementation, embedded firmware, system bring-up, validation, and cross-functional debug.\nThe successful candidate will work closely with FPGA architecture, board design, silicon engineering, software, and Altera development kit teams to deliver robust development kits, validation boards, and platform-level enablement for next-generation Altera FPGA devices.\nWhat You Will Do\nDefine, architect, design, implement, and validate FPGA RTL solutions using Verilog and/or VHDL for platform hardware, development kits, and validation boards.\n\nLead the complete FPGA development flow, including design planning, simulation, synthesis, implementation, timing analysis, timing closure, configuration, and release readiness using Altera Quartus II tools.\n\nDevelop and maintain embedded firmware in C and/or C++ for FPGA-based systems, with particular emphasis on the Nios II soft-core processor and associated peripherals.\n\nUse the Altera Embedded Design Suite (EDS) alongside the Altera Quartus II development flow to build, debug, integrate, and validate Nios II-based embedded applications and software components.\n\nTranslate system, functional, and performance requirements into scalable RTL, register maps, firmware interfaces, and verification strategies.\n\nSupport board bring-up, FPGA configuration, hardware-software integration, system initialization, and feature enablement on development and validation platforms.\n\nPlan and execute simulation, lab validation, stress testing, interoperability testing, and system-level debug using oscilloscopes, logic analyzers, protocol analyzers, and other laboratory equipment.\n\nInvestigate complex issues across RTL, firmware, FPGA timing, board interfaces, clocking, resets, memory, and peripheral integration; drive root-cause analysis and corrective actions.\n\nDevelop reusable RTL blocks, firmware components, test utilities, diagnostic tools, and automation scripts to improve platform development and validation efficiency.\n\nCollaborate with architecture, board design, silicon, software, applications, and system engineering teams to resolve technical issues and reduce platform risks.\n\nReview technical designs, RTL, firmware, verification plans, timing reports, lab data, and issue-tracking records; provide technical guidance to less-experienced engineers.\n\nDocument RTL designs, interfaces, test procedures, debug findings, validation results, and release criteria in accordance with Altera engineering standards.\n\nMinimum Qualifications\n· Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree is a plus.\n· 10+ years of professional experience in FPGA RTL design, implementation, and system-level validation.\n· Strong hands-on experience with Verilog and/or VHDL, digital logic design, computer architecture, clock-domain crossing, reset design, and FPGA-based system integration.\n· Proven experience with the Altera Quartus II FPGA development flow, including simulation, synthesis, implementation, timing analysis, timing closure, and device programming.\n· Working knowledge of C and/or C++ for embedded firmware, hardware-software integration, diagnostics, or platform validation.\n· Experience developing or integrating firmware for the Nios II soft-core processor, including peripheral access, interrupt handling, memory-mapped I/O, drivers, or board-support software.\n· Practical experience with the Altera Embedded Design Suite (EDS) for Nios II software development, build, debug, and integration.\n· Demonstrated ability to bring up and debug FPGA development boards or complex hardware platforms using lab equipment and structured debug methods.\n· Strong analytical, problem-solving, communication, and technical documentation skills.\n· Ability to work effectively across global, cross-functional engineering teams and independently drive deliverables to completion.\nPreferred Qualifications\n· Experience with Nios II system architecture, Platform Designer/Qsys integration, custom IP, Avalon interfaces, DMA, memory controllers, and peripheral subsystems.\n· Experience creating RTL-to-firmware interfaces, register specifications, device drivers, diagnostics, and automated validation tools.\n· Knowledge of FPGA configuration, boot flows, JTAG, PCIe, Ethernet, DDR memory, high-speed serial interfaces, or other board-level interfaces.\n· Familiarity with SystemVerilog, assertion-based verification, or other modern verification techniques.\n· Experience with Python, Tcl, or similar scripting languages for build automation, regression, test execution, report generation, and lab automation and Agentic AI knowledge for massive efficiency improvements.\n· Experience with version-control systems, continuous integration, code review, issue tracking, and disciplined hardware/software release processes.\n· Experience leading technical reviews, mentoring engineers, coordinating cross-functional debug, and communicating status and risks to program stakeholders.\nQualifications:\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; advanced degree is a plus.\n\n10+ years of professional experience in FPGA RTL design, implementation, and system-level validation.\n\nStrong hands-on experience with Verilog and/or VHDL, digital logic design, computer architecture, clock-domain crossing, reset design, and FPGA-based system integration.\n\nProven experience with the Altera Quartus II FPGA development flow, including simulation, synthesis, implementation, timing analysis, timing closure, and device programming.\n\nWorking knowledge of C and/or C++ for embedded firmware, hardware-software integration, diagnostics, or platform validation.\n\nExperience developing or integrating firmware for the Nios II soft-core processor, including peripheral access, interrupt handling, memory-mapped I/O, drivers, or board-support software.\n\nPractical experience with the Altera Embedded Design Suite (EDS) for Nios II software development, build, debug, and integration.\n\nDemonstrated ability to bring up and debug FPGA development boards or complex hardware platforms using lab equipment and structured debug methods.\n\nStrong analytical, problem-solving, communication, and technical documentation skills.\n\nAbility to work effectively across global, cross-functional engineering teams and independently drive deliverables to completion.\n\nPreferred Qualifications\nExperience with Nios II system architecture, Platform Designer/Qsys integration, custom IP, Avalon interfaces, DMA, memory controllers, and peripheral subsystems.\n\nExperience creating RTL-to-firmware interfaces, register specifications, device drivers, diagnostics, and automated validation tools.\n\nKnowledge of FPGA configuration, boot flows, JTAG, PCIe, Ethernet, DDR memory, high-speed serial interfaces, or other board-level interfaces.\n\nFamiliarity with SystemVerilog, assertion-based verification, or other modern verification techniques.\n\nExperience with Python, Tcl, or similar scripting languages for build automation, regression, test execution, report generation, and lab automation and Agentic AI knowledge for massive efficiency improvements.\n\nExperience with version-control systems, continuous integration, code review, issue tracking, and disciplined hardware/software release processes.\n\nExperience leading technical reviews, mentoring engineers, coordinating cross-functional debug, and communicating status and risks to program stakeholders.\n\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":8513,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Malaysia","iso":"MY","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-09-08T23:13:22Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.577,"p_room":0.55,"age_days":66,"expected_fill_days":53,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-11-14T05:58:10Z"},"pay":null,"html_url":"https://alion.io/job/altera-senior-fpga-rtl-and-firmware-development-engineer","json_url":"https://alion.io/job/altera-senior-fpga-rtl-and-firmware-development-engineer.json","meta":{"generated_at":"2026-11-15T01:30:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2834,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5328},"rest":"https://alion.io/mcp/rest/get_company?id=5328"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Faltera-senior-fpga-rtl-and-firmware-development-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Faltera-senior-fpga-rtl-and-firmware-development-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Faltera-senior-fpga-rtl-and-firmware-development-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/altera-senior-fpga-rtl-and-firmware-development-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Faltera-senior-fpga-rtl-and-firmware-development-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":557248}},{"tool":"search_jobs","arguments":{"company":"altera.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":557248},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}