{"id":3763143,"url":"https://alion.io/job/altera-senior-lead-design-engineer","title":"Senior Lead Design Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":17,"ghost_share":0,"stale_share":0.471,"repost_share":0.118,"time_to_fill_p50_days":53,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":330000,"currency":"USD","period":"year","gross":null,"usd_annual":330000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-04T19:13:10Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-05T18:51:04Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Details:\nJob Description:\nAbout the Role\nAltera is seeking a Senior Lead Design Engineer to provide hands-on technical leadership for the architecture, design, and delivery of next-generation FPGA and programmable SoC solutions. This is a senior individual-contributor/technical leadership role for an engineer who can influence technical direction across complex subsystems, product generations, and global engineering teams.\nIn this role, you will lead the definition and implementation of high-performance digital logic and reusable IP for programmable devices and platform solutions. You will translate product and system requirements into scalable architectures, drive key design decisions, and guide execution from early concept through RTL delivery, validation, and product readiness. The successful candidate will bring deep experience in complex ASIC, SoC, or FPGA development, a rigorous approach to design quality, and the ability to deliver impactful solutions for data center, networking, AI, and edge applications.\nResponsibilities\nLead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, with emphasis on high-throughput datapaths, connectivity, interconnect, memory access, or programmable acceleration.\nDefine technical requirements, interfaces, architectural specifications, and implementation plans that align hardware, firmware, software, validation, and product objectives.\nDrive technical tradeoffs across performance, power, area, latency, bandwidth, reliability, scalability, cost, and schedule; use data and analysis to identify and mitigate execution risk.\nOwn critical blocks and subsystems through the full development lifecycle, including RTL implementation, synthesis, integration, verification support, timing closure, bring-up, performance characterization, and issue resolution.\nEstablish and scale reusable design IP, coding standards, automation, and quality methodologies that improve engineering velocity, portability, predictability, and first-pass success.\nPartner with architecture, design verification, physical design, DFT, CAD, firmware, software, emulation, FPGA prototyping, board, and post-silicon teams to ensure architectural intent is maintained through product delivery.\nLead resolution of complex cross-functional design and system issues, including root-cause analysis, debug strategy, and technical decision-making.\nProvide technical mentorship and design leadership across teams; raise the engineering bar through architecture reviews, code reviews, and constructive technical guidance.\nInfluence engineering roadmaps and collaborate with internal teams and external partners on IP, tools, and technology choices that strengthen Altera’s programmable technology portfolio.\nWhat You Will Bring\nYou are a hands-on design leader who pairs strong technical depth with broad systems perspective. You bring sound engineering judgment, a high bar for quality, and a collaborative leadership style that helps teams solve complex problems and deliver differentiated programmable solutions. You are motivated by enabling customers to create what is next with Altera technology.\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231,500 - $330,000 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development; advanced degree preferred.\nDemonstrated technical leadership delivering complex digital subsystems or products from system architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.\nDeep hands-on expertise in Verilog and/or SystemVerilog RTL design, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices.\nProven experience with high-performance digital architectures, such as networking or packet-processing datapaths, offload or acceleration engines, PCIe/CXL, Ethernet, DDR/HBM memory subsystems, high-speed interfaces, or on-chip interconnect.\nStrong understanding of performance, power, area, timing, bandwidth, latency, congestion, and reliability tradeoffs in advanced digital systems.\nExperience leading design execution across multiple functional blocks or chip-level integration, including planning, risk management, schedule alignment, and technical prioritization.\nDemonstrated ability to collaborate and influence across architecture, RTL, verification, physical design, CAD, firmware/software, system validation, and product engineering organizations.\nStrong written and verbal communication skills, with the ability to clearly communicate architecture, design intent, technical risks, and recommendations to diverse audiences.\nPreferred Qualifications\nExperience in FPGA architecture, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.\nExperience building or maintaining reusable design IP deployed across multiple products, programs, or technology nodes.\nExperience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.\nProficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.\nExperience leading teams or serving as a senior technical mentor in a matrixed engineering environment.\nRecord of innovation through patents, publications, standards contributions, or technical thought leadership.\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, 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