{"id":3763144,"url":"https://alion.io/job/altera-senior-lead-engineer-design-and-architecture","title":"Senior Lead Engineer - Design and Architecture","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":16,"ghost_share":0,"stale_share":0.563,"repost_share":0,"time_to_fill_p50_days":53,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":330000,"currency":"USD","period":"year","gross":null,"usd_annual":330000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true}],"status":"closed","first_seen_at":"2026-11-04T19:13:10Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-11T12:39:32Z","board_verified":false,"closed_at":"2026-11-11T12:39:32Z","days_open":6,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":6},"description":"Job Details:\nJob Description:\nAbout the Role\nAltera is seeking a Senior Lead Engineer, Design and Architecture to provide technical leadership for the architecture and development of high-performance silicon and platform subsystems across our programmable device portfolio. This is a senior individual-contributor role for a hands-on architect and design leader who can define complex SoC and interconnect solutions, drive critical design decisions, and guide execution from early concept through production silicon.\nThe successful candidate will bring deep expertise in ASIC/SoC architecture, high-bandwidth interconnect, memory systems, and networking or infrastructure-class silicon. They will partner closely with architecture, RTL design, verification, emulation, physical design, software, and post-silicon teams to deliver scalable, performant, and manufacturable solutions for AI, cloud, networking, and edge applications.\nResponsibilities\nDefine system, subsystem, and microarchitecture for complex SoC, ASIC, and FPGA-adjacent platforms, with emphasis on high-performance interconnect, data movement, memory hierarchy, and scalable compute or networking subsystems.\nLead architecture exploration and make technically sound tradeoffs across performance, power, area, bandwidth, latency, reliability, scalability, cost, and schedule.\nDevelop architectural specifications, performance models, and implementation plans that align requirements across hardware, firmware, software, validation, and product teams.\nOwn key architecture and design decisions through the full silicon lifecycle: concept, microarchitecture, RTL, integration, verification, emulation, implementation, bring-up, performance debug, and production readiness.\nProvide hands-on technical leadership for on-chip networks, routing and arbitration, flow control, cache or memory-coherency mechanisms, memory subsystems, and high-speed interfaces, as applicable to the product roadmap.\nDrive cross-functional resolution of complex technical issues, using data and rigorous analysis to identify root cause, evaluate alternatives, and close critical architectural or execution risks.\nPartner with design, verification, physical design, DFT, firmware, software, product engineering, and manufacturing teams to ensure architecture intent is preserved through implementation and silicon validation.\nEstablish and improve scalable design and verification methodologies, automation, and quality practices that increase engineering velocity, predictability, and first-pass silicon success.\nMentor senior engineers and technical leads, raise the technical bar through reviews and design guidance, and influence engineering direction across multiple teams and product generations.\nEngage with internal and external partners, including IP, EDA, and foundry providers, as needed to inform architecture, implementation strategy, and roadmap planning.\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231,500 - $330,000\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with 15+ years of experience in semiconductor, ASIC, SoC, or FPGA product development.\nDemonstrated experience defining and delivering complex silicon architectures from concept through production, including architecture, microarchitecture, RTL design, verification, integration, and post-silicon validation.\nDeep expertise in one or more of the following: on-chip networks, coherent or non-coherent interconnect, memory hierarchy, cache coherency, high-performance networking datapaths, packet processing, or infrastructure-class SoC design.\nStrong understanding of architectural tradeoffs involving bandwidth, latency, congestion, throughput, power, area, timing, and reliability.\nExperience working across the silicon development lifecycle with design, verification, emulation, physical design, DFT, firmware/software, and post-silicon teams.\nProven technical leadership in driving complex cross-functional decisions, resolving ambiguous problems, and influencing engineering teams without direct management authority.\nPreferred Qualifications\nMaster’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nExperience delivering advanced-node, high-complexity SoCs or ASICs into production for networking, cloud, AI/ML, communications, storage, security, or data-center infrastructure applications.\nExperience architecting scalable Network-on-Chip or fabric solutions, including topology, routing, arbitration, quality of service, traffic management, credit-based flow control, and performance analysis.\nExperience with memory systems, cache hierarchy, coherency protocols, HBM/DDR integration, or high-bandwidth data movement.\nWorking knowledge of RTL and verification methodologies, such as SystemVerilog, simulation, formal verification, emulation, or equivalence checking, and familiarity with synthesis, static timing, and implementation flows.\nExperience with architecture modeling, performance analysis, Python-based automation, or AI-assisted engineering workflows that improve specification quality, debug, or design productivity.\nExperience with programmable logic devices, heterogeneous SoC platforms, or the integration of hard and soft IP across multiple product generations.\nRecord of technical innovation demonstrated through patents, publications, major product contributions, or industry leadership.\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, 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