{"id":3804286,"url":"https://alion.io/job/altera-senior-lead-engineer-design-verification","title":"Senior Lead Engineer - Design Verification","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":87,"open_postings":18,"ghost_share":0,"stale_share":0.444,"repost_share":0.111,"time_to_fill_p50_days":53,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":330000,"currency":"USD","period":"year","gross":null,"usd_annual":330000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C++","optional":true},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemC","optional":true}],"status":"live","first_seen_at":"2026-11-05T12:56:27Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-08T10:23:08Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nAbout the Role\nAltera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for the verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role will shape verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations.\nIn this role, you will define scalable verification strategies, develop reusable verification environments, and drive coverage-driven closure from early architecture through silicon and product readiness. The successful candidate combines deep SystemVerilog/UVM expertise with strong technical judgment, a high bar for verification quality, and the ability to influence engineering execution across global, cross-functional teams.\nResponsibilities\nLead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.\nDefine comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives.\nArchitect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.\nEstablish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs.\nDrive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria.\nPartner closely with architecture and RTL design teams to clarify specifications, identify verification risks early, review microarchitecture, and resolve complex functional or performance issues.\nLead debug of difficult simulation, integration, and system-level failures; apply rigorous root-cause analysis and drive timely resolution across design, verification, firmware, and validation teams.\nDevelop and maintain scalable simulation, regression, build, and reporting infrastructure to support efficient development and release quality.\nCollaborate with emulation, FPGA prototyping, physical design, CAD, firmware, software, board, and post-silicon teams to ensure verification intent is carried through implementation, bring-up, and product delivery.\nProvide technical mentorship and verification leadership through methodology reviews, test-plan reviews, code reviews, and hands-on guidance to engineers across the organization.\nWhat You Will Bring\nYou are a hands-on verification leader who combines deep technical expertise with a practical, systems-level perspective. You bring disciplined engineering judgment, a collaborative leadership style, and a passion for building the verification foundations that enable Altera to deliver differentiated, high-quality programmable solutions.\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231,500 - $330,000 USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, with 15+ years of relevant experience in design verification for FPGA, ASIC, SoC, or semiconductor products; advanced degree preferred.\nDemonstrated technical leadership delivering verification for complex digital subsystems or products from architecture through RTL verification, integration, full-chip verification, and hardware or silicon validation.\nDeep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking environments, testbench architecture, functional coverage, and coverage-driven closure.\nProven experience creating reusable verification IP, UVM frameworks, testbench components, or methodology adopted across multiple blocks, teams, or programs.\nExperience verifying high-performance digital architectures such as networking or packet-processing datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration.\nStrong understanding of RTL design, microarchitecture, simulation, debug, formal or static verification concepts, and hardware development flows.\nExperience with regression management, simulation build and execution flows, test automation, and data-driven verification reporting.\nDemonstrated ability to collaborate and influence across architecture, RTL design, CAD, emulation, firmware/software, system validation, and product engineering organizations.\nStrong written and verbal communication skills, with the ability to clearly communicate verification strategy, risk, closure status, and technical recommendations to diverse audiences.\nPreferred Qualifications\nExperience verifying FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.\nExperience with C/C++, SystemC, Python, Tcl, Perl, or shell scripting for reference models, automation, testbench infrastructure, or verification productivity.\nExperience with formal verification, low-power verification, CDC/RDC analysis, performance verification, or hardware-accelerated verification environments.\nExperience with full-chip verification, processor-based test development, firmware/software co-verification, or post-silicon debug.\nExperience leading verification methodology or mentoring engineers in a matrixed engineering environment.\nA record of innovation through patents, publications, standards contributions, or sustained methodology leadership.\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, 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