{"id":1494500,"url":"https://alion.io/job/altera-senior-principal-engineer","title":"Senior Principal Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":91,"open_postings":16,"ghost_share":0,"stale_share":0.125,"repost_share":0.063,"time_to_fill_p50_days":84,"computed_at":"2026-09-30T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States","United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":231500,"max":304500,"currency":"USD","period":"year","gross":null,"usd_annual":304500},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Machine Learning","optional":true}],"status":"live","first_seen_at":"2026-09-29T00:00:00Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-09-30T11:27:54Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nAltera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies.\nThe ideal candidate will have a proven track record of architecting and delivering breakthrough technologies that significantly improve quality of results (QoR), runtime, scalability, and customer productivity for large-scale FPGA or ASIC designs.\nThis role offers the opportunity to influence the long-term technical direction of Altera's FPGA software platform and collaborate with world-class engineers solving some of the industry's most complex optimization challenges.\nKey Responsibilities\nDefine and drive the architectural roadmap for FPGA compiler technologies.\nDesign and develop advanced optimization algorithms focused on timing closure, area reduction, power optimization, routability, and runtime improvement.\nLead development of next-generation timing driven optimization methodologies.\nArchitect scalable solutions for large hierarchical designs and complex FPGA implementation flows.\nDrive innovation across synthesis, placement, routing, timing analysis, and physical optimization domains.\nPartner with cross-functional engineering teams to integrate new technologies into production tool flows.\nAnalyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities.\nLead technical investigations of challenging timing and implementation problems across customer designs.\nMentor engineers and provide technical leadership across architectural and algorithmic initiatives.\nCollaborate with product management and strategic customers to translate market needs into differentiated technology solutions.\nContribute to patents, publications, and industry-leading innovations that strengthen Altera's competitive position.\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$231.5K - $304.5K USD\nWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nMinimum Qualifications\nBS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field.\n15+ years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies.\nDeep expertise in one or more of the following domains: Physical Synthesis Timing Analysis Logic Synthesis Placement and Routing Design Optimization Algorithms FPGA Architecture and CAD Flows Static Timing Analysis Physical Design Implementation\nDemonstrated experience architecting large-scale software systems and optimization engines.\nStrong software development skills in C++, data structures, algorithms, and performance optimization.\nProven ability to solve highly complex technical problems and deliver innovative solutions to production software environments.\nExperience influencing technical direction across multiple engineering teams.\nPreferred Qualifications\nExperience developing commercial FPGA or ASIC implementation tools.\nExpertise in path-based optimization, timing-driven synthesis, or physical design methodologies.\nExperience improving tool QoR, runtime performance, or scalability for large customer designs.\nBackground creating novel optimization algorithms that became widely adopted production technologies.\nExperience with machine learning applications for EDA optimization and implementation flows.\nPatent portfolio or significant technical publications in EDA, FPGA, or semiconductor design.\nExperience serving as a Distinguished Engineer, Architect, Fellow, or equivalent technical leadership role.\nWhat You'll Impact\nThe next generation of Altera FPGA implementation technologies.\nCore algorithms that directly influence customer design performance and productivity.\nStrategic roadmap decisions for synthesis, timing closure, and physical optimization.\nTechnical mentorship and engineering excellence across the organization.\nInnovation that differentiates Altera's FPGA software platform in an increasingly competitive market.\nAt Altera, you'll work alongside elite engineers solving some of the most challenging problems in semiconductor design automation while helping shape the future of programmable computing.\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nColorado, United States (Remote)Posting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":5385,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-09-30T01:44:04Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":84,"reasons":["conf:4","velocity","win:early","comp:brand"],"computed_at":"2026-09-30T05:45:00Z"},"pay":{"stated_usd_annual":304500,"is_top_pay":true},"html_url":"https://alion.io/job/altera-senior-principal-engineer","json_url":"https://alion.io/job/altera-senior-principal-engineer.json","meta":{"generated_at":"2026-10-01T00:44:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":511,"day_limit":5000,"remaining_today":4489,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}