{"id":34554,"url":"https://alion.io/job/altera-soc-frontend-integration-engineer","title":"SOC Frontend Integration Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":17,"ghost_share":0,"stale_share":0.471,"repost_share":0.118,"time_to_fill_p50_days":53,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-07-01T00:00:00Z","employer_posted_date":"2026-07-01","last_verified_at":"2026-11-07T07:23:39Z","board_verified":true,"closed_at":null,"days_open":129,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":129},"description":"Job Details:\nJob Description:\nWe are looking for energetic & experienced SoC Frontend Integration Engineer at various level to be part of our growing team to drive the frontend integration of complex System-on-Chip (SoC) FPGA designs. In this role, you will own top-level SoC RTL integration and drive quality, scalability, and robustness across multiple IPs and subsystems.\nYou will work cross-functionally with architecture, IP design, verification, reliability, timing/power, physical design, and post-silicon teams, playing a critical role in taking SoCs from concept to tapeout.\nKey Responsibilities\nConstruct SoC frontend RTL integration, assembling internal and third-party IPs into top-level SoC designs\nOwn SoC top-level RTL, hierarchy, connectivity, and scalability strategy\nDrive SoC-level frontend quality checks and closure\nPartner closely with verification teams to enable SoC-level simulation, emulation, and regression environments\nCollaborate closely with software team to enable integration of SoC into Quartus\nProvide high-quality frontend handoff to various SoC teams to enable other various checkouts like physical integration, timing/power convergence, pinout development, and reliability assessments.\nDebug and resolve complex integration issues across RTL, verification, and downstream flows\nReview IP deliverables and influence interfaces, clocking, reset, and power requirements\nPromote SoC integration best practices\nContinuously improve SoC integration flows, automation, and documentation\nQualifications:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field\n\nExperience with RTL design and integration using Verilog/SystemVerilog\n\nKnowledge various RTL quality checks required such as Lint, CDC/RDC, logical verification compile, emulation are required\n\nSolid understanding of SoC architectures and IP-based design methodologies\n\nExperience running and debugging frontend quality checks (lint, CDC, RDC)\n\nComfortable working in a Linux environment and using scripting languages (Perl, Python, Tcl, or Shell)\n\nStrong debugging, problem-solving, and cross-functional communication skills\n\nKnowledge in AI/ML SoC to improve productivity in SoC Integration are advantageous\n\nJob Type:\nRegularShift:\nShift 1 (Malaysia)Primary Location:\nPenang 15, Penang, MalaysiaAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or 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