{"id":131173,"url":"https://alion.io/job/altera-transceivers-protocol-ip-application-engineer","title":"Transceivers & Protocol IP Application Engineer","company":{"id":5328,"name":"Altera","domain":"altera.com","url":"https://alion.io/company/altera","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":13,"ghost_share":0,"stale_share":0.385,"repost_share":0.077,"time_to_fill_p50_days":60,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Backend","role_family":"Backend","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":149100,"max":215900,"currency":"USD","period":"year","gross":null,"usd_annual":215900},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Siemens ModelSim","optional":true}],"status":"live","first_seen_at":"2026-08-26T00:00:00Z","employer_posted_date":"2026-08-26","last_verified_at":"2026-10-25T21:23:12Z","board_verified":true,"closed_at":null,"days_open":60,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":60},"description":"Job Details:\nJob Description:\nAltera is seeking a technically strong Transceivers & Protocol IP Application Engineer to be based in San Jose California Altera Office to help customers and partners successfully adopt Altera FPGA transceiver and protocol IP solutions. This role serves as a trusted technical advisor across the customer design cycle-from architecture and IP selection through implementation, hardware bring-up, validation, optimization, and production readiness.\nThe engineer will work closely with regional application engineering, sales, silicon design, IP development, software, validation, documentation, and product teams. The role combines hands-on FPGA design and debug with customer communication, technical leadership, and product improvement.\nKey Responsibilities\nProvide expert technical guidance on Altera high-speed transceiver PHYs and protocol IP, including architecture, IP configuration, clocking, reset, PLL/CDR behavior, channel placement, link bring-up, and system integration.\n\nSupport customer designs using protocols such as Ethernet, PCIe, JESD204B/JESD204C, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, SerialLite, and PMA/FEC Direct PHY configurations, as applicable to the assigned product portfolio.\n\nReview customer system architectures, schematics, constraints, RTL, IP parameterization, simulation results, timing reports, and hardware measurements; identify risks and recommend practical corrective actions.\n\nReproduce and isolate customer issues using Quartus Prime, design examples, System Console, Signal Tap, Transceiver Toolkit, simulation environments, development kits, and laboratory equipment.\n\nDiagnose problems spanning FPGA IP, transceiver configuration, firmware, reference clocks, signal integrity, resets, data paths, protocol behavior, Quartus flows, and customer application logic.\n\nOwn technical cases from initial analysis through resolution, maintaining clear problem statements, evidence, investigation plans, customer updates, and closure documentation.\n\nCollaborate with engineering teams to escalate suspected product, IP, silicon, software, or documentation defects with sufficient reproduction data and technical analysis.\n\nDrive issue resolution and corrective actions, including improvements to design examples, user guides, application notes, knowledge-base content, tools, and customer workflows.\n\nProvide technical training, workshops, design reviews, demonstrations, and hands-on enablement for customers, partners, sales teams, field application engineers, and internal engineering teams.\n\nParticipate in product pre-enablement and release readiness activities; evaluate new devices, transceiver features, protocol IP releases, and customer use cases before broad deployment.\n\nCommunicate customer feedback and recurring technical issues into product definition, usability, validation, documentation, and future IP requirements.\n\nDevelop scripts, test collateral, reference designs, and automation in Python, Tcl, Bash, or similar languages to improve debug efficiency and customer adoption.\n\nContribute to a globally coordinated support model by sharing expertise, consulting with peers, and mentoring engineers in transceiver and protocol-IP domains.\n\nSalary Range\nThe pay range below is for Bay Area California only. Actual salary may vary based on a number offactors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.\n$149.1K- $215.9KUSD\nWe use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.\nQualifications:\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.\n\nProfessional experience in FPGA applications, high-speed digital design, ASIC/FPGA validation, protocol IP development, field application engineering, or technical customer support.\n\nHands-on experience with FPGA design flows and hardware debugging using Quartus Prime or a comparable FPGA development environment.\n\nWorking knowledge of high-speed serial interfaces, transceiver PHY concepts, clocking, PLLs, CDRs, resets, equalization, link training, channel bonding, and signal-integrity fundamentals.\n\nExperience reading and debugging RTL, IP configuration files, timing constraints, simulation waveforms, register maps, and hardware logs.\n\nProficiency in at least one hardware description language, such as Verilog, SystemVerilog, or VHDL.\n\nScripting or software-development experience in Python, Tcl, Bash, C, or C++.\n\nStrong analytical, problem-solving, prioritization, and technical writing skills.\n\nAbility to communicate clearly with customers and cross-functional engineering teams, including when the root cause is still under investigation.\n\nAbility to manage multiple technical issues and priorities while maintaining ownership, responsiveness, and high-quality records.\n\nPreferred Qualifications\nExperience with Altera Agilex, Stratix, Arria, or Cyclone FPGA families and associated transceiver tiles or PHY architectures.\n\nKnowledge of Ethernet MAC/PCS/FEC, PCIe, JESD204, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, or other high-speed protocol IP.\n\nExperience with Quartus Prime Pro, Platform Designer, System Console, Signal Tap, Transceiver Toolkit, ModelSim, Questa, or similar EDA and debug tools.\n\nExperience performing board-level bring-up, eye-diagram or BER analysis, loopback testing, protocol analysis, or lab-based transceiver characterization.\n\nExperience creating customer-facing documentation, training material, application notes, reference designs, or design examples.\n\nExperience working with regional application engineering, field application engineering, silicon, IP, software, validation, and technical communications organizations.\n\nWillingness to travel occasionally for customer meetings, workshops, design reviews, or hardware bring-up support.\n\nJob Type:\nRegularShift:\nShift 1 (United States of America)Primary Location:\nSan Jose, California, United StatesAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.","description_format":"text","description_chars":6643,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-08-26T00:00:00Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 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