{"id":2515966,"url":"https://alion.io/job/ambarella-asic-design-engineer-ii","title":"ASIC Design Engineer II","company":{"id":1908827,"name":"Ambarella","domain":"ambarella.com","url":"https://alion.io/company/ambarella","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":11,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":130000,"max":160000,"currency":"USD","period":"year","gross":null,"usd_annual":160000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Assembly","optional":false},{"name":"Perl","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T00:00:00Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-15T19:09:32Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"AI Vision Processors For Edge Applications\nOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.\nJob Description\nJob Description\nKey Responsibilities:\nPosition Responsibilities:\nDesign and implement video compression, image processing, vector processing, neural network accelerators, processor cores, and memory subsystems using Verilog and SystemVerilog. Perform logic design, implementation, and verification utilizing Verilog, SystemVerilog, and relevant programming and scripting languages. Synthesize and optimize RTL for performance, area, and power efficiency. Develop and enhance front-end design methodologies and tool flows. Contribute to chip bring-up and validation efforts. Analyze code and functional coverage metrics, and collaborate with the verification team to identify and address coverage gaps.\nQualifications:\nMaster’s degree in Electrical, Electronics, or Computer Engineering, with 0-5 years of relevant experience. Solid understanding of computer architecture, logic design, and VLSI design principles. Proficiency in SystemVerilog, Verilog, and Perl. Familiarity with design verification methodologies and functional coverage concepts. Experience with scripting languages and the ability to write assembly language programs. Strong communication skills and a collaborative, team-oriented mindset. Demonstrated problem-solving skills and analytical thinking. Knowledge of logic synthesis and timing closure is a plus.\nWhy Join Us?\nWork on industry-leading products in an innovative and collaborative environment.\n\nMake a direct impact on technologies used in autonomous vehicles, smart cameras, and more.\n\nCompetitive compensation, excellent benefits, and career development opportunities.\n\nThe base range is $130,000 -$160,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits. 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