{"id":1296744,"url":"https://alion.io/job/ambarella-asic-design-engineer-intern","title":"ASIC Design Engineer Intern","company":{"id":1908827,"name":"Ambarella","domain":"ambarella.com","url":"https://alion.io/company/ambarella","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":91000,"max_usd":235000,"period":"year","method":null,"sample_n":2006},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Assembly","optional":false},{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-26T00:00:00Z","employer_posted_date":"2026-08-26","last_verified_at":"2026-09-27T03:43:38Z","board_verified":true,"closed_at":null,"days_open":32,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":32},"description":"AI Vision Processors For Edge Applications\nOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.\nJob Description\nJob Description\nPosition Responsibilities:\nDesigning and implementing video compression logic, image processing logic, neural network and AI accelerator logics, and processor cores, in Verilog and System Verilog.\nLogic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.\nSynthesize and optimize RTL for timing, area and power.\nDeveloping unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.\nDeveloping test plan, random and directed test cases, performing logic verification, and functional coverage analysis.\nDeveloping front-end methodologies and tool flows.\nParticipating in chip bring-up and testing.\nRequirements:\nMaster’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.\nGood understanding of computer architecture, logic design and VLSI design.\nKnowledge of System Verilog, Verilog, and Perl.\nKnowledge of design verification, and functional coverage.\nAbility to program scripting languages and the ability to write assembly language programs.\nStrong communication skills and a good team player.\nKnowledge of logic synthesis and timing closer","description_format":"text","description_chars":1415,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Hardware","Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-09-26T09:36:35Z"}],"liveness":{"score":20,"band":"cold","label":"Long shot","p_open":1,"p_active":0.446,"p_room":0.45,"age_days":32,"expected_fill_days":21,"reasons":["conf:1","win:tail","comp:junior"],"computed_at":"2026-09-27T04:49:25Z"},"pay":null,"html_url":"https://alion.io/job/ambarella-asic-design-engineer-intern","json_url":"https://alion.io/job/ambarella-asic-design-engineer-intern.json","meta":{"generated_at":"2026-09-27T04:49:25Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4186,"day_limit":5000,"remaining_today":814,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}