{"id":1296761,"url":"https://alion.io/job/ambarella-sr-asic-design-engineer","title":"Sr. ASIC Design Engineer","company":{"id":1908827,"name":"Ambarella","domain":"ambarella.com","url":"https://alion.io/company/ambarella","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":14,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":135000,"max":170000,"currency":"USD","period":"year","gross":null,"usd_annual":170000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"AI Agents","optional":false},{"name":"Assembly","optional":false},{"name":"Edge AI","optional":false},{"name":"LLM","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2025-08-14T00:00:00Z","employer_posted_date":"2025-08-14","last_verified_at":"2026-10-30T23:16:57Z","board_verified":true,"closed_at":null,"days_open":443,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":443},"description":"AI Vision Processors For Edge Applications\nOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.\nJob Description\nPosition Responsibilities:\nDesigning and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference-alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.\nLogic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.\nSynthesize and optimize RTL for timing, area, and power.\nExplore micro-architecture and architectural tradeoffs via quick modelling using scripting languages such as python, Perl etc.\nDeveloping unit level test environments and tests cases\nDeveloping front-end methodologies and tool flows.\nParticipating in chip bring-up and testing.\nAnalyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.\nRequirements:\nMaster’s degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.\nGood understanding of computer architecture, logic design and VLSI design.\nKnowledge of System Verilog, Verilog, python, and Perl.\nKnowledge of design verification, and functional coverage.\nAbility to program in scripting languages and the ability to write assembly language programs.\nStrong communication skills and a good team player.\nAdept problem-solving abilities\nKnowledge of logic synthesis and timing closer is a plus\nThe base salary range is $135,000 - $170,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.The successful candidate will have the opportunity to convert to a full-time regular position. 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