{"id":1296750,"url":"https://alion.io/job/ambarella-vlsi-design-verification-engineer-2","title":"VLSI Design Verification Engineer_2","company":{"id":1908827,"name":"Ambarella","domain":"ambarella.com","url":"https://alion.io/company/ambarella","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":9,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-29T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":87000,"period":"year","method":null,"sample_n":2549},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-07-16T00:00:00Z","employer_posted_date":"2026-07-16","last_verified_at":"2026-09-27T10:14:08Z","board_verified":false,"closed_at":null,"days_open":76,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":76},"description":"AI Vision Processors For Edge Applications\nOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.\nJob Description\nWe are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug.\nResponsibilities\nDevelop and execute verification plans for complex SoCs/IPs\nBuild testbenches, assertions, and coverage models\nCollaborate with architects, designers, and post-silicon teams\nEnsure correctness and reliability of cutting-edge designs Why Join Us\nCutting-edge verification with AI-powered flows\nWork alongside global world-class engineers\nAccelerated growth in a learning-driven culture If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation!\nQualifications\nBachelor’s, Master’s, or PhD in EE/CS or related field\nStrong background in digital design and computer architecture\nExperience with SystemVerilog/UVM/Verilog/C/C++ (script with Perl/Python is a plus)\nStrong debugging, analytical, and problem-solving skills","description_format":"text","description_chars":1240,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Hardware","Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-09-26T09:36:35Z"}],"liveness":{"score":12,"band":"cold","label":"Long shot","p_open":1,"p_active":0.34,"p_room":0.35,"age_days":75,"expected_fill_days":21,"reasons":["conf:43","velocity","win:tail"],"computed_at":"2026-09-29T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/ambarella-vlsi-design-verification-engineer-2","json_url":"https://alion.io/job/ambarella-vlsi-design-verification-engineer-2.json","meta":{"generated_at":"2026-09-30T02:22:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1631,"day_limit":5000,"remaining_today":3369,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}